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15
TK-3212/3217
A beat sound may be able to be evaded from generation if
“Beat Shift” is set to ON when it is generated in the internal
spurious transmission modulated sound of a transceiver.
2) Memory Circuit
Memory circuit consists of the CPU (IC405) and an EEPROM
(IC406). An EEPROM has a
capacity of 64k bits that contains
the transceiver control program for the CPU and data such
as transceiver channels and operating features.
CIRCUIT DESCRIPTION
Channel selector
CPU
IC405
SIDE 2
EN2
EN1
71
49
PTT
PTT
SW
SIDE 1
27
74
75
SW1
SW2
Fig. 11 Control system
7. Control System
LCD, Keys and channel selector circuit.
The signal from keys and channel selector input to
microprocessor directly as shown in fig. 11.
3) Low Battery Warning
The battery voltage is checked by the microprocessor.
The transceiver generates a warning tone when the battery
voltage falls below the warning voltage (2) shown in the
table.
(1) The red LED blinks when the battery voltage falls below
the voltage (1) shown in the table during transmission.
Transmission is still allowed.
Note:
The transceiver checks the battery voltage during reception
even when, in the FPU, the Battery Warning status function
is set to “While Transmitting” (default setting).
However, the LED does not blink during reception. The red
LED blinks during transmission. The transceiver is still
usable.
(2) The transceiver immediately stops transmission when
the battery voltage falls below the voltage (2) shown in
the table. A warning tone sounds while the PTT switch
is pressed.
IC405
CPU
IC406
EEPROM
Fig. 9 Memory circuit
11
8
XOUT
BSHIFT
IC405
Q407
H:OFF
L : ON
Q408
H:OFF
L : ON
X3
Fig. 8 Frequency shift circuit
SB
R404
R406
BATT
IC405
CPU
88
Fig. 10 Low battery warning
Ni-MH Battery
(1)
6.2[V]
(2)
5.8[V]