TK-280
31
SEMICONDUCTOR DATA
Voltage Detector : RN5VL42C
(TX-RX Unit : IC3)
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Block diagram (CMOS output)
VCO System : X58-4580-10 (SUB Unit : A1)
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Circuit diagram
Counter : MC74HC4017F (Display Unit : IC301)
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Logic circuit
●
Input
CLOCK (pin No.14) - Clock Input
The rising edge of this clock advances the count.
●
Controller Input
RESET (pin No.15) - Asynchronous Reset Input
When this pin is High, the counter is initialized. and Q0 and
CARRY OUT output become High. At this time, Q1 to Q9
become Low.
CLOCK ENABLE (Pin No.13) - Clock Enable Input (Low active)
The count operation is forbidden when this pin is High. When
it is Low. the normal count is carried out. When the clock
input (pin No.14) is used as enable (High active). this input
can be used for the count as the rising clock.
●
Output
Q0 to Q9 (pins 3,2,4,7,10,1,5,6,9,11) - Decoded Decade
Counter Output
These outputs become High only during a single clock cycle.
CARRY OUT (pin No.12) - Cascade Output Pin
This output is used as the cascade output, or as the
÷
10
output during the 50% duty cycle. When the count reaches
"5", this output becomes Low. When the count reaches "0"
or is reset, this output becomes High. When counters are
cascade-connected, this output sends the rise signal to clock
input of the next counter.
1
OUT
Output.
2
V
DD
Power supply.
3
GND
Ground.
Pin No.
Pin code
Function
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Pin function
X58-4580-10 SUB UNIT
