Kenwood RXD-DV9, Руководство по обслуживанию

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RXD-DV9
8
CIRCUIT DESCRIPTION
Pin No. Pin Name I/O Description
83 CP1 - RC connection terminal of RC value of peak hold, for RFRP generation.
84 MIRRI I Input terminal for MIRR signal generation.
85 EQVCC - Power voltage input signal for RF EQ.
86 RFEQ0 O RF EQ output terminal.
87 BCATH I BCA comparating level control terminal.
88 EQIN I RFAGCO input terminal for RF EQ.
89 RFAGCO O RF AGC AMP output terminal.
90 AGCC - CAP connection terminal for time constant of AGC.
91 AGCI I AGC voltage input terminal while in AGC hold.
92 EQGND - Power ground input terminal for RF EQ.
93 AGCLEVEL I AGC level control voltage input terminal(3.5V) while in AGC hold off.
94 AGCB - RC connection terminal for RC value of bottom hold, for RF AGC.
95 AGCP - RC connection terminal for RC value of peak hold, for RF AGC.
96 RDPF - Bias resistance connection terminal for selecting RF EQ frequency.
97 EQG I RF EQ boost gain control voltage input terminal.
98 EQF I RF EQ peak frequency control voltage input terminal.
99 PLLF I Wide-band PLL compatible RF EQ peak frequency control terminal.
100 VZOCTL I RF EQ zero control terminal.
Pin No. Pin Name I/O Description
1 D GND - Digital ground.
2 DPS CS I Chip select(active low).
3 HAD I Micom resistor select (L resistor data).
4 D GND - Digital ground.
5~12 HAD7~HAD0 I/O Micom data bus.
13 DVDD - Digital power(+5.0V).
14 CLK27D I System clock input for 26.16MHz.
15 XTO1 O System clock output for 26.16MHz.
16 D GND - Digital ground.
17 DD15 I/O DRAM data bus.
18 DD0 I/O DRAM data bus.
19 DD14 I/O DRAM data bus.
20 DD1 I/O DRAM data bus.
21 D GND - Digital ground.
22 DD13 I/O DRAM data bus.
23 DD2 I/O DRAM data bus.
24 DD12 I/O DRAM data bus.
25 DD3 I/O DRAM data bus.
26 DVDD - Digital power(+5.0V).
27 DD11 I/O Digital data bus.
28 DD4 I/O Digital data bus.
29 DD10 I/O Digital data bus.
30 DD5 I/O Digital data bus.
31 D GND - Digital ground.
32~35 DD9~DD7 I/O DRAM data bus.
36 D GND - Digital ground.
37 ZLCAS O DRAM low column address strobe.
38 ZUCAS O DRAM upper column address strobe.
39 ZWE1 O DRAM write enable 1(8M only).
40 ZWE0 O DRAM write enable 0(4M,8M,16M ).
41 ZOE1 O DRAM output enable 1(16M mode DADR9 ).
42 DVDD - Digital power(+5.0V).
43 ZOE O DRAM output enable 0.
44 ZRAS O DRAM low address strobe.
45,46 DADR8,DADR7 O DRAM address bus.
47 D GND - Digital ground.
3. Pin descrption of data processor DIC1(KS1453)
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