RD-HD5MD/HD7
12
CIRCUIT DESCRIPTION
Pin No.
Pin Name
I/O
Pin Description
Active
H
L
37
TRCRS
I
Track cross signal input pin (analog input).
38
RFDET
I
RF detector signal input pin.
Detected
39
BDO
I
Drop out signal input.
Drop Out
40
LDON
O
Laser on signal output.
ON
41
PLLF2
I/O PLL loop filter switching pin.
42
TOFS
O
Tracking offset adjusting output.
43
WVEL
O
Double speed status signal output.
Double
Speed
44
ARF
I
RF signal input.
45
IREF
I
Reference current input pin.
46
DRF
I
DSL bias pin.
47
DSLF
I/O DSL loop filter pin.
48
PLLF
I/O PLL loop filter pin.
49
VCOF
I/O VCO loop filter pin.
50
AVDD2
-
Analog power supply for DSL, PLL, and DA output section.
51
AVSS2
-
Analog ground for DSL, PLL, and DA output section.
52
EFM/CK384
O
EFM signal output when IOSEL is H.
16.9344MHz clock output when IOSEL is L.
53
PCK/DSLB
O
PLL clock output (fPCK = 4.3218MHz) or DSL balance output.
54
VCOF2
I/O Jitter free VCO loop filter pin.
55
SUBC
O
Sub code serial output.
56
SBCK
I
Clock input for sub code serial output.
57
VSS
-
GND
58
X1
I
Crystal oscillation circuit input. f =16.9344MHz, 33.8688MHz
59
X2
O
Crystal oscillation circuit output. f =16.9344MHz, 33.8688MHz
60
VDD
-
Power supply for crystal oscillation circuit.
61
BYTCK
O
Bite clock signal output when IOSEL is H.
Stop Mode
Traverse stop signal output when IOSEL is L.
General IO pin when default.
62
CLDCK
O
Sub code frame clock signal output (fCLDCK = 7.35kHz) when
command is carry out.
General IO pin when default.
63
FCLK
O
Crystal frame clock signal output (fFCLK = 7.35kHz) when
command is carry out.
64
IPFLAG
O
Interpolation flag signal output.
65
FLAG
O
Flag signal output.
66
CLVS
O
Spindle servo phase synchronism signal output.
CLV
67
CRC
O
Sub code CRC checked output.
OK
NG
68
DEMPH
O
De-emphasis detection signal output.
ON
Re-frame synchronism signal RESY output of frame synchronism
69
RESY
O
when IOSEL is H.
H : Synchronized L : Non synchronized
70
IOSEL
I
Switching pin for mode.
71
TEST
I
Test pin.
Normal
72
AVDD1
-
Analog power supply for audio output section.
73
OUTL
O
L ch audio output.
74
AVSS1
-
Analog ground for audio output section.
75
OUTR
O
R ch audio output.
• RF signal polarity assignment pin when default.
RSEL is H when bright level is H.
76
RSEL
I
RSEL is L when bright level is L.
• General IO pin when command is executed.
RF signal polarity assignment is set by command.