
KTC-HR100
2
BLOCK DIAGRAM
SDRAM
DSP
FPGA
FLASH ROM
70.56MHz
DEMODULATOR
43.20MHz
IC4
X1
IC1
IC6
IC7
IC2
A1
CN2
CN1
CN5
CN1
CN2
to EXTERNAL UNIT
CN3
CN4
(+1.25V)
3.3V 7724
(+3.3V)
3.3V DSP
(+2.5V)
2.5V FPGA
(+3.3V)
1.25V DSP
F/E
A1
CF1,3
ANTENNA
(OPTION)
SWITCH
FILTERS &
EEPROM
IC15
u-COM
IC11
IC5
AMP
SW
IC2
BUFFER
IC7
AMP
IC3,4
to WRITER
CN6
to HOST PC
CN2
to CONT
J4
to H/U
J2
to CD-CH
RCA
J1
J3
(5L BUS)
(5L BUS)
20.00MHz
X1
REGULATOR
IC1
IC6
IC14
IC17
IC12
Q8,L2,3
IC9
+8V
+3.3V
+2.5V
+1.25V
+8.5V
+5V
REGULATOR
REGULATOR
REGULATOR
REGULATOR
BU5V
DCDC-
CONVERTER
to H/U
J2
SIGNAL
CONTROL
CLOCK
RECEIVER
(ANALOG)
(DIGIT
AL)
A
UDIO
I2C
IF OUT
IF OUT
IF OUT(DIGITAL)
IF OUT(ANALOG)
A
UDIO
UA
R
T
I2C
BU
POWER SUPPLY
(X32-5510-10)
(X14-9310-10)
POWER SUPPLY (X14-9310-10)