13
KRF-V6200D/V7200D
Pin No.
Pin Name
I/O
Description
33
FILT1
-
External fi lter for PLL
34
VA
-
Power supply for clock generator (+2.5V)
35
AGND
-
Ground for PLL of clock generator
36
/RESET
I
Master reset input port
37
DD
-
Pulled up
38
DC
-
Pulled up
39
AUDATA2
O
Digital audio output port-2
40
AUDATA1
O
Digital audio output port-1
41
AUDATA0
O
Digital audio output port-0
42
LRCLK
I/O
Audio output sampling rate clock
43
SCLK
I
Audio output bit clock
44
MCLK
I/O
Audio master clock
*book referred to maker's semiconductor handbook
●
LC72725KV (IC761: X08) Port Description
Pin No.
Pin Name
I/O
Description
1
RDS-ID/READY
O
RDS-ID/READY output
2
RDDA
O
RDS data output
3
Vref
O
Standard voltage output (Vdda/2)
4
MPXIN
I
Base band (MPX) input
5
Vdda
-
Analog power supply (+3V)
6
Vssa
-
Analog gnd.
7
FLOUT
O
Sub carrier output (Filter output)
8
CIN
I
Sub carrier input (Comparator input)
9
TEST
I
Test signal input
10
MODE
I
Read mode setting (0: master, 1: slave)
11
Vssd
-
Digital gnd.
12
Vddd
-
Digital power supply (+3V)
13
XIN
I
Crystal oscillator input (External standard signal input)
14
XOUT
O
Crystal oscillator output (4.332MHz)
15
RST
I
RDS-ID/RAM reset
16
RDCL
I/O
RDS clock output (master), RDS clock input (slave)
*book referred to maker's semiconductor handbook
No
ITEM
INPUT SETTING
OUTPUT SETTING
RECEIVER
SETTING
ALIGNMENT POINT
ALIGNMENT
SETTING
FIG.
1
IDLE CURRENT
(BIAS CURRENT)
No Signal
Connect VOM to
CN7 (L-ch) or
CN6 (R-ch)
X09-703
VOLUME:
Minimum
VR3 (L-ch)
VR4 (R-ch)
X09-703
17.6mV
2
OFFSET
No Signal
Speaker terminals
VOLUME:
Minimum
VR1 (L-ch)
VR2 (R-ch)
X09-703
0+-20mV
Adjust every potentiometers 10 minutes later after turning on.
ADJUSTMENT
CIRCUIT DESCRIPTION / ADJUSTMENT
