7
KDC-8026/MP825
KDC-MPV8025/W7027
Pin No.
Pin Name
I/O
Description / Processing Operation
83
NOISE
I
FM noise detection terminal
84
IFC OUT
I
Front end IFC OUT input terminal (Receiving station : 2.5V or more)
85
POWER DET
I
Audio power IC DC offset detection
86
CD SW4
I
8cmDISC detection terminal (8cmDISC : L)
87
R CLK
I
RDS decoder clock input terminal
88
LX REQ S
I
Receive request from external slave unit (Request : L)
89
SC REQ
I
Communication request from panel microprocessor
90
CD SW1
I
LOADING SW detection terminal (LOADING start, POWER OFF : L)
91
CD SW2
I
12cmDISC detection terminal (12cmDISC, POWER OFF : L)
92
R QUAL
I
RDS decoder QUAL input terminal
93
R DATA
I
RDS decoder DATA input terminal
94
LX DATA S
I
Data input from external slave unit
95
LX DATA M
O
Data output to external slave unit
96
LX CLK
I/O
Clock input/ output with external slave unit
97
L DATAL
I
Data input from LCD driver
98
L DATAS
O
Data output to LCD driver
99
L CLK
O
CLK output to LCD driver
100
PLL CLK
I/O
Clock input/ output to Tuner front-end
Fig.1 FPM motor control
SLIDE
FPM mechanism
FPM MOTOR B
FPM MOTOR F
operation
L
L
Standby
H
L
Backward operation
L
H
Forward operation
H
H
Brake
ANGLE
FPM mechanism
FPM MOTOR O
FPM MOTOR C
operation
L
L
Standby
H
L
Angle open direction
L
H
Angle close direction
H
H
Brake
MICROCOMPUTER’S TERMINAL DESCRIPTION
●
MECHANISM CONTROL MICROPROCESSOR : 91CW12AFG-4VF6 (X32-554 : IC1)
Pin No.
Pin Name
I/O
Description / Processing Operation
1
VREFL
I
Reference voltage input terminal
2
AVSS
-
GND for ADC
3
AVCC
-
Power supply for ADC (BU3.3V)
4
NC
O
NC (OPEN)
5
20RST
O
Reset control output terminal (for decoder) L : RESET, H : NORMAL
6
20ACK
I
Acknowledge signal input terminal (for decoder)
7
20STBY
O
Standby control (for decoder) H : STAND BY, L : NORMAL
8,9
NC
O
NC (OPEN)
10
20INT
I
Interrupt signal input terminal (for decoder)
11
FOGUP
I
Interrupt for focus gain up control signal H : Focus gain UP, L : NORMAL