Kenwood GX-608EF2, Руководство по обслуживанию

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GX-608EF2
7
Pin Function I/O Description Processing Operation
1 BDO I Dropout signal input H: detected (Photodetector signal input 1)
2 OFT I Off track signal input H: detected (Photodetector signal input 2)
3 /RFDET I RF detection signal input H: detected (Photodetector signal input 3)
4 VDET I Vibration detection signal input H: detected (Photodetector signal input 4)
5 LDON O Laser on signal output H: ON (Photodetector RF signal adding input)
6 NC - No connection (RF amplifier filter terminal 1)
7 NC - No connection (RF amplifier filter terminal 2)
8 AVSS3 I Analog circuit GND
9 AVDD3 I Analog circuit power supply
10 FBAL O Focus balance adjustment output Laser diode monitor input
11 TBAL O Tracking balance adjustment output Laser diode drive output
12 FE I Focus error signal input (DA input)
13 NC - No connection (Tracking filter filter terminal 1)
14 NC - No connection (Tracking filter filter terminal 1)
15 TE I Tracking error signal input (analog input)
16 NC - No connection (Track cross comparator filter terminal)
17 NC - No connection
18 NC - No connection RF signal input (for RF detection)
19 RFENV I RF envelop signal input
20 VREF I VREF input terminal
21 ARF I RF signal input (for DSL)
22 DRF I DSL bias terminal
23 DSLF I/O DSL loop filter terminal
24 IREF I Reference voltage input terminal
25 PLLF I/O PLL loop filter terminal
26 PLFF2 I/O PLL loop filter properties switching terminal
27 VCOF I/O VCO loop filter terminal
28 VCOF2 I/O Digital servo 33.8688 MHz generating
VCO loop filter terminal
29 TRV O Traverse forced feeding output
30 TVD O Traverse drive output
31 PC O Spindle motor on detection L: ON
32 ECM O Spindle motor drive output (forced mode output)
(DA output)
33 ECS O Spindle motor drive output
(Servo error signal output)
34 KICK O Kick pulse output
35 TRD O Tracking drive output
36 FOD O Focus drive output
37 TOFS O Tracking offset adjustment output
38 AVDD2 I Analog circuit power supply
(for DSL, PLL, AD and DA sections)
39 AVSS2 I Analog circuit GND
(for DSL, PLL, AD and DA sections)
40 DVSS2 I Digital circuit GND
41 EFM or CK384 O EFM signal output Default : EFM signal output
When command executed : 16.9344 MHz clock
output
42 PCK or DSLB O PLL sampling clock output Default : PLL sampling clock output
When command executed : DSL balance output
43 /CLDCK O Subcode frame clock signal output
44 FCLK O Crystal frame clock signal output
45 IPFLAG O Interpolation flag signal output H: interpolation
46 FLAG O Flag signal output
47 TRCRS O Track cross signal input (Track cross signal output)
MICROCOMPUTER'S TERMINAL DESCRIPTION
MECHANISM MICROCOMPUTER : MN662770KA7 (IC2 : X32-4600-00)
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Terminal Description