DV-505/DVF-4050/-S
6
CIRCUIT DESCRIPTION
Port No.
Port Name
I/O
Main Function
Alternate function
Input
Output
12
PIO3(6)
I/O
Unused
PARA DATA(6)/
UART1 CTS(CTS1)
COMP OUT1
13
PIO3(7) DVD RESET
I/O
PIO3(7)
PARA DATA(7)/
UART2 CTS(CTS2)
COMP OUT0
39
PIO4(0)HP MUTE
-
Unused
40
PIO4(1)
-
Unused
41
PIO4(2)
-
Unused
42
PIO4(3) DAC RESET
-
Unused
43
PIO4(4) PLL CS
-
Unused
44
PIO4(5) DAC CLOCK
O
DAC clock
45
PIO4(6) DAC DATA
O
DAC data
46
PIO4(7) DAC CS
I/O
PIO4(0~7)
YC(0~7)
Reserved
20
B WCLK
I/O
Unused
21
B V4
I/O
Connected to GND
22
NRSS OUT
I/O
Unused
103
ADC SCLK
I/O
Unused
104
ADC LRCK
I/O
Unused
105
ADC DATA
I/O
Unused
106
ADC PCMCLK
O
Unused
EMI Interface
161~170 CPU ADR(1~10)
O
ADR(1~10)
173~183 CPU ADR(11~21)
O
ADR(11~21)
141~148 CPU DATA(0~7)
I/O
DATA(0~7)
151~158 CPU DATA(8~15)
I/O
DATA(8~15)
138
CPU RAS1
I/O
Unused
131
CPU WAIT
I
Connected to GND
130
CPU RW
O
Unused
128
CPU BE(0)
O
BYTE 0 ENABLE
129
CPU BE(1)
O
BYTE 1 ENABLE
139
CPU CAS0
O
Unused
140
CPU CAS1
O
Unused
135
CPU CE(0)
O
Unused
134
CPU CE(1)
O
Unused
133
CPU CE(2)
O
Chip Sel. BANK2
132
CPU CE(3)
O
Chip Sel. BANK3
118
CPU PRO CLK
O
SDRAM clock
117
CPU OE
I/O
Output enable
Interrupt
127
IRQ(0)
I
Unused
126
IRQ(1)
I
Unused
125
IRQ(2)
I
IRQ(2) (MD IRQ)
Timers
116
PWM0
I/O
Unused
HSYNC
115
PWM1
I/O
Pulse width modula o
Boot from ROM3
114
PWM2
I/O
Unused
VSYNC
JTAG
113
TCK
I
Test clock
112
TDI
I
Test data in
111
TDO
O
Test data out
110
TMS
I
Test mode select
109
TRST4
I
Test reset
Front-end
16
B DATA
I
12S data
SER Data
17
B BCLK
I
12S bit clock
SER BCLK
