Kenwood DVF-3060, Руководство по обслуживанию

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DVF-3060/3060-S/3060K-S
7
CIRCUIT DESCRIPTION
Pin No. Pin Name I/O Pin Description
1~8 A15~A8 I Address Inputs
9,10 N.C. - Unused
11 WE - Write Enable
12 RP - Reset/Block Temporary Unprotect
13,14 N.C. - Unused
15 RY/BY O Ready/Busy/Output
16,17 A18,A17 I Address Inputs
18~25 A7~A0 I Address Inputs
26 CE - Chip Enable
27,46 VSS - Ground
28 QE - Output Enable
29~36
DQ0~DQ15 I/O Data Input/Outputs, Command Inputs
38~45
37 VCC - Supply Voltage
45 DQ15 I/O Data Input/Outputs or Address input
47 BYTE - Byte/Word Organization
48 A16 I Address Inputs
A Q
L H
H L
Pin No. Pin Name I/O Pin Description
1,3,5,9,11,13 A0 to A5 I Data Inputs
2,4,6,8,10,12 Q0 to Q5 O Data Outputs
7 GND - Ground
14 VCC - Positive Supply Voltage
Truth Table 2-2 HEX Inverter (Single Stage) : M74HCU04(IC51)
2-3 Flash Memory : M29W 800AT
Pin No. Pin Name I/O Pin Description
1 GND - Ground
2 VO1 O Output 1
3 VCTL I Motor speed control
4 VIN1 I Input 1
5 VIN2 I Input 2
6 SVCC - Supply voltage (Signal)
7 PVCC - Supply voltage (Power)
8 VO2 O Output 2
2-4 DC Motor Driver : KA8082(IC23)
Pin No. Pin Name I/O Pin Description
1,14,27, VCC - Power supply for internal circuits and input buffers.
2,4,5,7,8,10
11,13,42,44 45, DQ0~DQ15 I/O Multiplexed data input/output pin.
47,48,5051,53
3,9,43,49 VCCQ - Power supply for output buffers.
6,12,46,52 VSSQ - Ground for output buffer.
15,39 LDQM,UDQM I/O Controls output buffers in read mode and masks input data in write mode.
16,17,18 WE,CAS,RAS - WE, CAS and RAS define the operation.
19 CS - Enables or disables all inputs except CLK, CKE, and DQM.
20,21 BA0,BA1 -
Selects bank to be activated during RAS activity.
Selects bank to be read/written during CAS activity.
22,23~26 A10, A0~A3
29~34,35 A4~A9, A11
- Address bus : A0~A11
28,41,54 VSS - Ground for internal circuits and input buffers.
36,40 NC - Unused.
37 CKE -
Controls internal clock signal and when deactivated, the SDRAM will be
one of the states among power down, suspend or self refresh.
38 CLK I
The system clock input. all other inputs are registered to the SDRAM on
the rising edge of CLK.
2-5 64 Bit SDRAM : HY57V641620HGT
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