DV-6050
17
CIRCUIT DESCRIPTION
Pin No.
Pin Name
I/O
Pin Description
47,49~52,54~56
HD0~HD15
I/O
DVD microcomputer data bus 0~15.
58~60,62,63,65~67
69
AUDSTR
I
Valid signal of bit stream input data.
70
VSTR
I
Clock signal input for bit stream.
71
VRQ
O
Request of program stream.
73~76,78~81
STD7~STD0
I
Bit stream parallel input 0~7.
83
IECOUT
O
IEC958 format data output.
84
DMIX
O
Down mix signal output (CH7/CH8).
86
DACCK
O
Over sampling DAC clock output.
87
LRCK
O
LR clock output.
88
SRCK
O
Bit clock output.
90~92
ADOUT(0~2)
O
Audio data output (0~2).
94
CLK121
I
External clock (121.5MHz) input. (Unused)
95
CKIO
I
"L" : Fixed
96
CLK27
I
System clock input (27MHz).
97
PLLVDD
-
Supply voltage (+1.8V) of internal logic for main PLL.
98
CLK81
-
Connected to digital ground.
100
EXTCK
I
Clock input for audio.
101
PLLAVDD
-
Main PLL supply voltage (+3.3V).
102
TCPOUT
0
Unused.
103
PLLAVSS
-
Ground for main PLL.
106
PHCOPMO
O
Audio PLL phase comparison output.
107
APLLVDD
-
Supply voltage (+1.8V) of internal logic for Audio PLL.
108
ACKIO
I
"L" : Fixed
109
MODE121
I
Switching port for SDRAM clock frequency.
110
DCTEST
I
DC test mode terminal.
111
APLLAVSS
-
Ground for audio PLL.
112
APLLAVDD
-
Supply voltage (+3.3V) for Audio PLL.
113
VREFCR
I
DAC reference voltage input for CR signal.
114
IREFCR
I
DAC bias current setting port for CR signal.
115
COMPCR
I
Capacitance connection for DAC (CR signal) stabilization.
116
VCROUT
O
CR signal output for DAC.
117,127
AVDD
-
Analog supply voltage (+3.3V) for DAC.
118
VREFC
I
DAC reference voltage input for C signal.
119
IREFC
I
DAC bias current setting port for C signal.
120
COMPC
I
Capacitance connection for DAC stabilization.
121
VCOUT
O
C signal output for DAC.
122,132
AVSS
-
Analog ground for DAC.
123
VREFCB
I
DAC reference voltage input for CB signal.
124
IREFCB
I
DAC bias current setting port for CB signal.
125
COMPCB
I
Capacitance connection for DAC (CB signal) stabilization.
126
VCBOUT
O
CB signal output for DAC.
128
VREFY
I
DAC reference voltage input for Y signal.
129
IREFY
I
DAC bias current setting port for Y signal.
130
COMPY
I
Capacitance connection for DAC (Y signal) stabilization.
131
VYOUT
O
Y signal output for DAC.
133,134
TESTSEL1,0
I
Test mode terminal.
L : Fixed
136
VCLK
O
Clock output for digital video data output.
137~140,142,143
REC(7~2)
I/O
REC656 input (7~2).
144
REC1
I/O
REC656 input 1. Vertical synchronizing signal input/output.
XVSYNCO
145
REC0
I/O
REC656 input 0. Horizontal synchronizing signal input/output.
XHSYNCO
147~150,152~155
VD0~VD7
O
Digital video data output (0~7).
