20
DDX8017/8027/8027Y
DDX8037/8047/8067
Pin No.
Pin Name
Module
I/O
Application
Processing Operation Description
82
WE3/DQMUU
EXTRA
O
D31~D24 select signal /DQM (SDRAM)
83
RDWR
EXTRA
O
Read/Write
84
VssQ
Power supply
-
85
CS0
EXTRA
O
Chip select 0 (ROM)
For ROM
86
VccQ
Power supply
-
I/O power supply
3.3V
87
CS2
EXTRA
O
Chip select 2 (For DMA)
88
CS3
EXTRA
O
Chip select 3 (SDRAM)
For SDRAM
89
CS4
EXTRA
O
Chip select 4 (SRAM)
For SRAM
90
CS5
EXTRA
O
Chip select 5 (GRiTT: VRAM)
For GRITT
91
CS6
EXTRA
O
Chip select 6 (GRiTT: Register)
For GRITT
92
NC
O
93
VssQ
Power supply
-
94
NC
O
95
VccQ
Power supply
-
I/O power supply
3.3V
96
RAS
EXTRA
O
Row address strobe
97
NC
O
NC
98
CAS
EXTRA
O
Colum address strobe
99
NC
O
100
CKE
EXTRA
O
Clock enable
101
SHINI
V850
I
Resetting start identification
H: Other than reset start, L: Reset start
102
BACK
EXTRA
O
Bus acknowledge
NC
103
BREQ
EXTRA
I
Bus right request
High level fixed.
104
R_WAIT
GRITT
I
Hardware wait request
105
SH_DACK
GRITT
O
DMA acknowledge
106,107
NC
O
108
SHSTBY
V850
O
Power supply OFF permission
H: Power supply OFF not permitted
L: Power supply OFF permitted
109
AUDATA0
H-UDI
I/O
AUDATA input/output
110
AUDATA1
H-UDI
I/O
AUDATA input/output
111
AUDATA2
H-UDI
I/O
AUDATA input/output
112
AUDATA3
H-UDI
I/O
AUDATA input/output
113
AUDSYN.C
H-UDI
O
AUDSYNC output (H-UDI)
114
TDI
H-UDI
I
Data input (H-UDI)
115
Vss
Power supply
-
116
TCK
H-UDI
I
Clock (H-UDI)
117
Vcc
Power supply
-
Internal power supply
1.9V
118
TMS
H-UDI
I
Mode select (H-UDI)
119
TRST
H-UDI
I
Reset (H-UDI)
120
TDO
H-UDI
O
Data output (H-UDI)
121
ASEBRKAK
H-UDI
O
ASE break acknowledge (H-UDI)
MICROCOMPUTER’S TERMINAL DESCRIPTION