Keithley PIO-96, Инструкция по эксплуатации

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B-2 I/O Address Map PIO-96 User’s Manual
Address offsets 0-3, 4-7, 8-11, and 12-15 correspond to the four 8255 PPI chips, each of which
has four ports: three I/O ports and one control port. Each of the 8255 chips acts identically and
independently. (For a full description of the many capabilities of the 8255 chip, refer to the data
sheet of Intel or other 8255 chip manufacturer.)
All the operating modes of the 8255 are supported identically on the PIO-96. However, the
majority of users are likely to operate the 8255 in the simple basic input/output mode (also
called Mode 0 operation). Therefore, only Mode 0 is emphasized here. If you wish to operate the
8255 in Mode 1 (strobed input/output) or Mode 2 (bidirectional bus) configurations, refer to the
8255 data sheet.
NOTE
On power up or whenever the computer RESET line is asserted, all I/O
ports of the 8255 are initially set as inputs.
Also, a write to the control register at base a3 (or +7, +11, or
+15) clears all output ports.
The 16 locations in I/O address space are allocated as shown in Table B-1.
Note that the PIO-96 requires a full block of sixteen I/O addresses. For correct operation, other
adapters must not conflict with any I/O address within this range, even if the upper ports of your
PIO-96 will not be used.
Table B-1
I/O address map
Bits Location Function Type
0-23 Base a0 8255 PA Port Read/Write
Base a1 8255 PB Port Read/Write
Base a2 8255 PC Port Read/Write
Base a3 8255 Control Write Only
24-47 Base a4 8255 PA Port Read/Write
Base a5 8255 PB Port Read/Write
Base a6 8255 PC Port Read/Write
Base a7 8255 Control Write Only
Base a8 8255 PA Port Read/Write
48-71 Base a9 8255 PB Port Read/Write
Base a10 8255 PC Port Read/Write
Base a11 8255 Control Write Only
Base a12 8255 PA Port Read/Write
72-95 Base a13 8255 PB Port Read/Write
Base a14 8255 PC Port Read/Write
Base a15 8255 Control Write Only