Keithley KPCI-PIO32IOA, Руководство пользователя

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KPCI-PIO32IOA and KPCI-PDISO8A User’s Manual I/O Address Mapping B-5
Interrupt example scenario
The following example is one possible scenario that may help you to understand and use the
KPCI-PIO32IOA and KPCI-PDISO8A interrupt feature. (This example is simplified, and some
details may not apply to your specific system or to your requirements.) It illustrates the workings
of the interrupts and bits 6, 12, 17, and 23 of the interrupt control/status register. (Refer also to
Section 4 , “ External Interrupts .”)
1. At some point, computer software sets interrupt-enable bit 12 of the interrupt control/status
register to logic-high. (The term “software” here refers to the combination of the application
programming interface (API)/driver—normally, DriverLINX—and the application program.
To understand how to program interrupt-triggered data acquisition through DriverLINX,
refer to your DriverLINX documentation.) This status, detected by board firmware, enables
the board to process data using external interrupts. It changes general-purpose inputs PC6
and PC7 of port group 3 into external interrupt request and external interrupt enable inputs
INT_REQ and INT_ENN.
2. At some point, computer software sets latching polarity bit 6 for port group 0 to determine
whether that data at port group 0 latches on the rising or falling edge of INT_REQ.
Table B-3
Bit functions for interrupt control/status register
Interrupt Control/Status Register Bit Status for this Bit
1
Bit
Number Bit Function
Where the Bit is Set
and Cleared When the Bit Value = 0 When the Bit Value = 1
Bit 06 Selects polarity for the
external interrupt signal. Set and cleared by
computer software. Sets rising edge for
external interrupt signal. Sets falling edge for
external interrupt signal.
Bit 12 Configures the board for
external interrupt service. Set and cleared by
computer software. Interrupts disabled. Data
transfer and processing via
polling or upon software
command, only. All inputs
are general purpose inputs. Interrupts enabled. Data
transfer and processing in
response to an external
signal, only. The highest
two inputs of port A are
INT_REQ and INT_ENN
instead of IP6 and IP7.
Bit 17 Interrupt-pending.
Indicates whether or not an
external interrupt signal
has been received at the
board INT_REQ input. Automatically set high
when board firmware
detects an interrupt. Must
acknowledge (write 1) to
clear. Register status awaits
detection of interrupt
signal by firmware.
Computer CPU is
presently doing other tasks
(not processing
KPCI-PIO32IOA or
KPCI-PDISO8A data). Interrupt signal has been
received. Computer CPU is
processing, or is about to
process, KPCI-PIO32IOA
or KPCI-PDISO8A data
via an ISR.
3
Bit 23 Interrupt-missed. Indicates
whether or not at least one
KPCI-PIO32IOA or
KPCI-PDISO8A external
interrupt signal has been
sent and missed while
interrupt-pending bit 17 is
high. Automatically set high
when board firmware
detects missed interrupt.
2
Must acknowledge (write
1) to clear.
Interrupts have not been
missed OR register status
awaits missed-interrupt
detection by firmware.
1
One or more interrupts
have been missed.
3
1
All bits listed in this table are cleared to logic-low on power-up.
2
Although this bit has both software read and software write capability, computer software writes should only be used to clear the bit.
3
This status is correct only if bit 17 is deliberately cleared by computer software at the conclusion of each board ISR (each ISR that is used to process board
data).