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Service Information
4-3
1. The ID DATA line (pin 5 of U107) is set from high to
low while the ID CLK line (pin 6 of U107) is held high.
This action initiates a start command to the ROM to
transmit data serially to the mainframe (Figure 4-3).
2. The mainframe sends the ROM address location to be
read over the ID DATA line. The ROM then transmits an
acknowledge signal back to the mainframe, and it then
transmits data at that location back to the mainframe
(Figure 4-4).
3. The mainframe then transmits an acknowledge signal,
indicating that it requires more data. The ROM will then
sequentially transmit data after each acknowledge sig-
nal it receives.
4. Once all data is received, the mainframe sends a stop
command, which is a low-to-high transition of the ID
DATA line with the ID CLK line held high (see
Figure 4-3).
ID CLK
ID DATA
START BIT
STOP BIT
Figure 4-3
Start and stop sequences
ID CLK
START
ACKNOWLEDGE
1
8
9
ID DATA
(DATA OUTPUT
FROM
MAINFRAME
OR ROM)
ID DATA
(DATA OUTPUT
FROM
MAINFRAME
OR ROM)
Figure 4-4
Transmit and acknowledge sequence
4.8
Output channel control
Digital output channels are controlled by serial data
transmitted from the mainframe to the I/O card via the
OUTDATA line. A total of fi e bytes (40-bits) are shifted in
a serial fashion into latches located in the output channel
driver ICs. The serial data is clocked in by the OUTCLK line.
As data overfl ws one register, it is fed out the Q’S line of the
register down the chain.
Once all fi e bytes have shifted into the card, the STROBE
line is set high to latch the output channel information into
the Q outputs of the output channel drivers. Note that a chan-
nel driver output goes low when it is turned on (closed).