4200-900-01 Rev. K / February 2017
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Model 4200-SCS User’s Manual
Section 3: Common Device Characterization Tests
Running any Flash Project for the first time
1. Connect up the 4200-SCS FLASH package, using the Flash Connections instructions for
one of the following configurations:
a. Direct connection (no switch matrix) to single DUT: Use
b. Direct connection (no switch matrix) to array DUT:
and
.
c. Switch matrix connection to array or single DUT: Use
2. See procedures below for using a specific Flash project.
a. Initial characterization using the
Running the Flash-NAND, Flash-NOR or Flash-Switch
b. Endurance or Disturb testing using the
Running a FlashEndurance or FlashDisturb
,
,
, or
.
Running the Flash-NAND, Flash-NOR or Flash-Switch Project
The Flash projects use a small number of tests and methods. This section will
explain the tests and how to set parameter values.
These projects allow initial characterization of a device, including the
determination of the pulse settings (pulse width, height, and transition time) that
will provide a target programmed or erased V
T
. After the appropriate pulse
settings are determined, they can be used to perform Endurance or Disturb
testing on the DUT.
1. If system connections have not been made, follow the instruction in
.
2. If KITE is not running, start KITE by double-clicking the KITE icon on the 4200-SCS
desktop.
3. Open the appropriate KITE Flash project.
a. Within KITE, click
FILE
>
Open Project
. If the dialog window is not displaying the
_Memory folder, move up one or two levels to the display the Projects directory.
b. Double-click the _Memory folder, then double-click the desired Flash test folder (Flash-
NAND, Flash-NOR or Flash-Switch)
c. Double-click the Flash-NAND.kpr, Flash-NOR.kpr or Flash-Switch.kpr file to open the
desired 4200-SCS Flash project. KITE should resemble
for Flash-Switch Project.
4. Touch-down or connect the DUT.
5. Verify setup and connection by running Vt-MaxGm test
a. Set appropriate voltages
b. Run the test by clicking the yellow and green triangle Append button.
c. Ensure that the V
G
-I
D
and V
T
results are reasonable.
6. Determine the appropriate pulse voltage levels.
Pulse waveforms for NVM testing
b. Recall that pulse voltage levels on the gate will double
i.
For example, using PulseVoltage = 2 will result in V
G
= 4 V for a typical high-impedance
(1 k Ω) terminal.
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