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Model 2657A High Power System SourceMeter® Instrument Reference Manual
Appendix E: Status model
2657A-901-01 Rev. B/December 2012
E-17
The bits of the Status Byte Register are described as follows:
•
Bit B0, Measurement Summary Bit (MSB):
Set summary bit indicates that an enabled
measurement event has occurred.
•
Bit B1, System Summary Bit (SSB):
Set summary bit indicates that an enabled system event
has occurred.
•
Bit B2, Error Available (EAV):
Set bit indicates that an error or status message is present in the
error queue.
•
Bit B3, Questionable Summary Bit (QSB):
Set summary bit indicates that an enabled
questionable event has occurred.
•
Bit B4, Message Available (MAV):
Set bit indicates that a response message is present in the
output queue.
•
Bit B5, Event Summary Bit (ESB):
Set summary bit indicates that an enabled standard event
has occurred.
•
Bit B6, Request Service (RQS)/Master Summary Status (MSS):
Set bit indicates that an
enabled summary bit of the Status Byte Register is set. Depending on how it is used, bit B6 of the
Status Byte Register is either the Request for Service (RQS) bit or the Master Summary Status
(MSS) bit:
•
When using the GPIB or VXI-11 serial poll sequence of the Model 2657A to obtain the status byte
(serial poll byte), B6 is the RQS bit. See
(on page E-18) for details on using the
serial poll sequence.
•
When using the *STB? common command or status.condition
Status byte and service request
(on page E-18) to read the status byte, B6 is the MSS bit.
•
Bit B7, Operation Summary (OSB):
Set summary bit indicates that an enabled operation event
has occurred.
Service Request Enable Register
The Service Request Enable Register controls the generation of a service request. This register is
programmed by the user and is used to enable or disable the setting of bit B6 (RQS/MSS) by the
Status Summary Message bits (B0, B1, B2, B3, B4, B5, and B7) of the Status Byte Register. As
shown in the
(on page E-15) topic, a logical AND
operation is performed on the
summary bits (&) with the corresponding enable bits of the Service Request Enable Register. When a
logical AND
operation is performed with a set summary bit (1) and with an enabled bit (1) of the
enable register, the logic “1” output is applied to the input of the logical OR gate and, therefore, sets
the MSS/RQS bit in the Status Byte Register.
The individual bits of the Service Request Enable Register can be set or cleared by using the
*SRE
common command or
status.request_enable
. To read the Service Request Enable Register,
use the
*SRE?
query or
print(status.request_enable)
. The Service Request Enable Register
clears when power is cycled or a parameter value of 0 is sent with a status request enable command
(for example, a
*SRE 0
or
status.request_enable = 0
is sent). The commands to program and
read the SRQ Enable Register are listed in
Status byte and service request commands
(on page E-
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