RTX Tiny
15
2
Requirements and Definitions
The following chapter describes the software and hardware requiremens of RTX51 Tiny
and defines the terms used within this manual. RTX51 Tiny uses a combination of system
calls as well as the
_task_
keyword for the task definition which is built in to the C51
compiler. The task definition and the major features of RTX51 Tiny are also described
within this chapter.
Development Tool Requirements
The following software products are required to operate RTX51 Tiny:
•
C51 Compiler
•
BL51 Code Banking Linker
•
A51 Macro Assembler
The library file
RTX51TNY.LIB
must be stored in the library path specified with the
DOS envirionment variable C51LIB. Usually this is the directory
C51\LIB
.
The include file
RTX51TNY.H
must be stored in the include path specified with the
DOS envirionment variable C51INC. Usually this is the directory
C51\INC
.
Target System Requirements
RTX51 Tiny can run on single-chip 8051 systems without any external data memory.
However the application can access external memory. RTX51 Tiny can use all memory
models supported by C51. The selected memory model only influences the location of
application objects. The RTX51 Tiny system variables and the stack area of the applica-
tion are always stored in internal 8051 memory (DATA or IDATA). Typically, RTX51
Tiny applications are implemented in the SMALL model.
RTX51 Tiny performs round-robin task switching only. Preemptive task switching and
task priorities are not supported. If your application needs preemptive task switching you
need to use the RTX51 Full Real-Time Executive.
RTX51 Tiny is not designed for use with bank switching programs. If you require
real-time multitasking in your code banking applications you need to use the RTX51 Full
Real-Time Executive.
Interrupt Handling
RTX51 Tiny can operate parallel with interrupt functions. Similar to other 8051 applica-
tions, the interrupt source must be enabled in the 8051 hardware registers in order to trig-
ger for an interrupt. RTX51 Tiny does not contain any management for interrupts; for
this reason, the interrupt enable is sufficient to process interrupts.
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