JYTEK Thunderbolt PXIe-62314T, Руководство пользователя

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22 Introduction
Reference Clock
The PXIe-62314T backplane supplies a single-ended 10MHz
reference clock (PXI_CLK10) and differential 100MHz clock
(PXIe_CLK100) to each peripheral slot for inter-module syn-
chronization. The independent buffers drive the clock signal to
each peripheral slot.
These common reference clock signals can synchronize multi-
ple modules in a PXI Express chassis. PXI modules with
phase-lock loop circuits can lock reference clocks to generate
an in-phase timebase.
The PXI_CLK10 and PXIe_CLK100 clocks are in-phase
according to the PXI-5 specification.