JYTEK PXIe-69529, Руководство пользователя

Страница: 18 / 28

12
Description Mi1LSB Midscale Midscale –1LSB
Bipolar Analog
Input 1.19 μV 0 V -1.19 μV
0.119 μV 0 V -0.119 μV
Digital Code 000001 000000 -FFFFFF
Table 3-2: Input Range Midscale Values
3�2�3 ADC and Analog Input Filter
ADC (Analog-to-Digital Converter)
The PXIe-69529 provides sigma-delta analog-to-digital converters, suitable for vibration,
audio, and acoustic measurement. Analog side of the sigma-delta ADC is 1-bit, and the
digital side performs oversampling, noise shaping and digital filtering. For example, if a
desired sampling rate is 108kS/s, each ADC samples input signals at 27.648MS/s, 256 times
the sampling rate. The 1-bit 27.648MS/s data streams from 1-bit ADC to its internal digital
filter circuit to produce 24-bit data at 108kS/s. The noise shaping removes quantization
noise from low frequency to high frequency. At the last stage, the digital filter improves ADC
resolution and removes high frequency quantization noise. The relationship between ADC
sample rate and DDS output clock is as follows.
Sampling Rate DDS(PLL) CLK
8k to 54kS/s 6.144 M~41.472 MHz
54K to 108kS/s 13.824 M to 27.648 MHz
108K to 192kS/s 20.736 M to 36.864 MHz
Table 3-3: ADC Sample Rates vs DDS Output Clock
Filter
Each channel has a two-pole lowpass filter. The filters limit bandwidth of the signal path and
reject wideband noise.
3�2�4 DMA Data Transfer
The PXIe-69529, as a PCIe Gen1 X 4 device, provides a 204.8 KS/s sampling rate ADC,
generating a 3.276 MByte/second rate. To provide efficient data transfer, a PCI bus-
mastering DMA is essential for continuous data streaming, as it helps to achieve the full
potential PCI Express bus bandwidth. The bus-mastering controller releases the burden on
the host CPU since data is directly transferred to the host memory without intervention.
Once analog input operation begins, the DMA returns control of the program. During DMA
transfer, the hardware temporarily stores acquired data in the onboard AD Data FIFO, and
then transfers the data to a user-defined DMA buffer in the computer.
Using a high-level programming library for high speed DMA data acquisition, the sampling
period and the number of conversions needs simply to be assigned into specified counters.