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2.4.3 Inhibit/Voltage Monitoring DB-9 Connector

The DB-9 connector monitors the four main power rails via digital multimeter. Power
rail pin assignments shown in Figure 15. There are 10 kΩ current-limiting resistors on
each power rail prevents accidental overload. One Inhibit (active low) pin is provided
to power the chassis on/off when the Inhibit Switch is in the MAN (manual) position,
such that chassis is powered on when Inhibit pin is logic high or open, and off when
Inhibit pin is grounded.

Figure 15 Inhibit/Voltage Monitoring DB-9 Connector

2.4.4 Inhibit Switch

In the

DEF

(default) position, the front panel power button turns the power supply

on/off, and in the

MAN

(manual) position, the

Inhibit

pin on the DB-9 connector

turns the power supply on/off.

Figure 16 Inhibit Switch

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Содержание PXIe-2722

Страница 1: ...PXIe 2722 Chassis User Manual User Manual Version V1 0 2 Revision Date Nov 8 2021...

Страница 2: ...rnment 11 Mechanical Dimensions 12 Front and Rear Panels 16 2 4 1 Front Panel 16 2 4 2 Rear Panel 17 2 4 3 Inhibit Voltage Monitoring DB 9 Connector 18 2 4 4 Inhibit Switch 18 2 4 5 FAN Switch 19 2 4...

Страница 3: ...JYTEK Software Platform 51 JYTEK Warranty and Support Services 51 8 Statement 52 Figure 1 PXIe 2722 Gen3 Backplane Architecture 2 Figure 2 PXIe 2722 Gen2 Backplane Architecture 3 Figure 3 PXIe 2722 P...

Страница 4: ...k source 42 Figure 35 Change PXI Trigger Manager Setting To JYTEK 43 Figure 36 Trigger Bus Routing Control 44 Figure 37 Install NI MAX 45 Figure 38 Change PXI Trigger Manager Setting 45 Figure 39 NI M...

Страница 5: ...el name Note system bandwidth defined as data rate between controller and chassis backplane slot bandwidth defined as data rate between peripheral module and chassis backplane Main Features PXI 5 PXI...

Страница 6: ...Backplane Architecture All of the PXIe peripheral slots can support PCIe Gen3 x8 link providing a maximum slot bandwidth of 8 GB s The system slot can support PCIe Gen3 x24 link x8 x16 and has a maxim...

Страница 7: ...our of the PXIe peripheral slots have a PCIe Gen2 x8 link providing a maximum slot bandwidth of 4 GB s The 13 remaining peripheral slots have a PCIe Gen2 x4 link providing a maximum slot bandwidth of...

Страница 8: ...rid peripheral slots It can accept the following peripheral modules PXI Express Peripheral Module CompactPCI Express Type 2 Peripheral Module Hybrid slot compatible PXI 1 Peripheral Module CompactPCI...

Страница 9: ...ger bus segment containing 8 trigger lines connecting all slots on the same segment providing inter module synchronization Trigger bus buffers can connect or disconnect the trigger lines of adjacent s...

Страница 10: ...SYNC100 to each peripheral slot for inter module synchronization The PXI_CLK10 and PXIe_CLK100 clocks are in phase according to the PXI 5 specification A phase lock loop PLL circuit on the backplane s...

Страница 11: ...PXIe 2722 Chassis jytek com 7 Figure 6 System Reference Clock Default Behavior...

Страница 12: ...PXIe 2722 Chassis jytek com 8 Specifications 2 2 1 Basic Table 3 Basic Specification...

Страница 13: ...PXIe 2722 Chassis jytek com 9 2 2 2 Electrical...

Страница 14: ...PXIe 2722 Chassis jytek com 10 Table 4 Electrical Specification 2 2 3 System Synchronization Clock...

Страница 15: ...PXIe 2722 Chassis jytek com 11 Table 5 System Synchronization Clock 2 2 4 Physical and Enviornment Table 6 Physical and Environment...

Страница 16: ...PXIe 2722 Chassis jytek com 12 Mechanical Dimensions All dimensions are shown in mm millimeters Figure 7 Front View Figure 8 Left Side View...

Страница 17: ...PXIe 2722 Chassis jytek com 13 Figure 9 Right Side View Figure 10 Rear View...

Страница 18: ...PXIe 2722 Chassis jytek com 14 Figure 11 Top View...

Страница 19: ...PXIe 2722 Chassis jytek com 15 Figure 12 Bottom View...

Страница 20: ...and Rear Panels 2 4 1 Front Panel Figure 13 Front Panel Location Feature 1 Chassis Model Name 2 Removable Feet 3 Backplane Connectors 4 Chassis Status LED 5 Power Switch 6 10MHz REF CLK IN 7 10MHz REF...

Страница 21: ...s jytek com 17 2 4 2 Rear Panel Figure 14 Rear Panel Location Feature 1 Chassis Ground Screw 2 FAN Switch 3 AC Input 4 Rear Output Vents 5 Inhibit Switch 6 Inhibit Voltage Monitoring DB 9 Connector Ta...

Страница 22: ...t active low pin is provided to power the chassis on off when the Inhibit Switch is in the MAN manual position such that chassis is powered on when Inhibit pin is logic high or open and off when Inhib...

Страница 23: ...hassis temperature Figure 17 FAN Switch 2 4 6 Chassis Status LED Table 9 Chassis Status LED 2 4 7 Fan Mode PXIe 2722 provides the smart fan control mechanism as blow curve It provides two fan modes Fa...

Страница 24: ...ed temperature less than 25 C and begin ramping up when any temperature reading exceeds 25 C Fans run at 100 duty cycle full speed if any temperature reading exceeds 50 C When the Fan Switch is set to...

Страница 25: ...PXIe 2722 Chassis jytek com 21 Note For details about chassis temperature monitoring please see JYDM utility on page 32...

Страница 26: ...ooling Considerations 2 5 1 PXI PXIe Modules Cooling For PXI PXIe modules cooling there are three fans on the rear panel draw cool air from the bottom side and front panel to be exhausted to the rear...

Страница 27: ...Chassis jytek com 23 2 5 2 Power Supply Cooling For power supply cooling power supply s fan draws cool air from the right side to be exhausted through the left side of the chassis Figure 21 Power Supp...

Страница 28: ...46H 109 MB s 3 PXI 69846H 109 MB s 4 PXI 69846H 109 MB s 5 PXI 69846H 109 MB s 6 PXI 69846H 109 MB s 7 PXI 69846H 109 MB s Segment 2 8 PXI 69846H 109 MB s 9 PXI 69846H 109 MB s 10 PXI 69846H 109 MB s...

Страница 29: ...PXIe 2722 Chassis jytek com 25 Figure 22 PCI Bus Throughput for segment 1...

Страница 30: ...PXIe 2722 Chassis jytek com 26 Figure 23 PCI Bus Throughput for segment 2...

Страница 31: ...PXIe 2722 Chassis jytek com 27 Figure 24 PCI Bus Throughput for segment 3...

Страница 32: ...PXIe 2722 Chassis jytek com 28 PCIe Bus Throughput 3 2 1 PXIe 2722G3 PCIe Bus Throughput Table 12 PXIe 2722G3 PCIe Bus Throughput...

Страница 33: ...PXIe 2722 Chassis jytek com 29...

Страница 34: ...987 has only 16GB s theoretical maximum bandwidth Slot 1 is the system bandwidth test its theoretical maximum bandwidth is 24 GB s PCIe Gen3 x24 Slot 2 to 18 are the slot bandwidth test its theoretica...

Страница 35: ...PXIe 2722 Chassis jytek com 31 3 2 2 PXIe 2722G2 PCIe Bus Throughput Table 13 PXIe 2722G2 PCIe Bus Throughput...

Страница 36: ...PXIe 2722 Chassis jytek com 32...

Страница 37: ...theoretical maximum bandwidth is 8 GB s PCIe Gen2 x16 Slot2 slot6 slot11 and slot15 can support PCIe Gen2x8 its theoretical maximum bandwidth is 4 GB s Other peripheral slots can support PCIe Gen2x4 i...

Страница 38: ...PXIe 2722 Chassis jytek com 34 Compatibility test...

Страница 39: ...PXIe 2722 Chassis jytek com 35...

Страница 40: ...PXIe 2722 Chassis jytek com 36 Table 14 Compatibility test...

Страница 41: ...management driver and firmware online upgrade online driver version management board test panel JYTEK SeeSharp card driver information view test panel Installation and use of JYDM JYDM support operat...

Страница 42: ...side of the JYDM interface is the hardware device column and the right side is the device details column You can view and configure the current device information and upgrade the driver and firmware F...

Страница 43: ...itoring the chassis power rails 5Vsb standby power 3 3V 5V 12V and 12V DC power Figure 27 Monitoring the Chassis Power Rails Monitoring the chassis temperature sensors T1 sensor is located on the top...

Страница 44: ...low user to control the cooling capability via JYDM Figure 30 Chassis Cooling Control in JYDM Target Temperature specifies the chassis temperature at which the maximum fan speed 100 duty cycle is achi...

Страница 45: ...rget temperature setting is 50 C User can change target temperature to lower value ex 40 C it will increase fan speed if the factory default setting could not fulfill the peripheral modules cooling re...

Страница 46: ...s On Board as shown in figure 33 Figure 33 Reference Clock Status Display for default setting If the external 10MHz clock input the chassis via SMA conncector it will override the onboard 10MHz clock...

Страница 47: ...to route these trigger lines in JYDM 1 Clicking on My System item set Default PXI Trigger Manger to JYTEK and then click Save to save the settings 2 Clicking on the PXI chassis branch and then click...

Страница 48: ...PXIe 2722 Chassis jytek com 44 Figure 36 Trigger Bus Routing Control...

Страница 49: ...0 0 or higher from NI website Figure 37 Install NI MAX Open JYDM set Valid PXI Resource Manager and Default PXI Trigger Manger to National Instruments and then click Save to save the settings Figure 3...

Страница 50: ...PXIe 2722 Chassis jytek com 46 Figure 39 NI MAX GUI display JYTEK chassis and modules...

Страница 51: ...n please visit our web www jytek com to download Using PXIe 2722 with National Instruments PXI PXIe Peripheral Modules 5 2 1 Use National Instruments PXI PXIe Peripheral Modules without synchronizatio...

Страница 52: ...2 Chassis jytek com 48 But you can use DAQmx Export Signal to set appointed clock trigger routing Figure 41 DAQmx Export Signal DAQ synchronization reference code Figure 42 DAQ Synchronization Referen...

Страница 53: ...Rack Mount Kits JYTEK provides optional hardware for installation of PXIe 2722 chassis into a server or rack The rack mounting kits dimension as following figure All dimensions are shown in mm millim...

Страница 54: ...ies JYTEK Korea was the first JYTEK enterprise outside China to promote JYTEK products Together with Adlink Technologies and JYTEK China JYTEK is expanding to more countries Each JYTEK location is an...

Страница 55: ...quisition JYTEK Software Platform JYTEK has developed a complete software platform SeeSharp Platform for the test and measurement applications We leverage the open sources communities to provide the s...

Страница 56: ...lectual property rights unless such disclaimer is legally invalid JYTEK is not responsible for any incidental or consequential damages related to performance or use of this manual The information cont...

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