JYTEK PCIe-69834, Руководство пользователя

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Operations 21
trigger events in each mode. Trigger events arriving too close to
the previous instance will be ignored by the digitizer.

In Post-Trigger mode, the minimum spacing between trigger
events is N+1

In Delayed-Trigger mode, the minimum spacing between
trigger events is (N+D)+1, where D is the number of the
delayed setting
Figure 3-9: Re-Trigger Mode Acquisition
3.5 Timebase
Figure 3-10: PCIe- 69834 Clock Architecture
CLK IN
80M Xtal
To ADC
Synthesizer
PLL Board
REF_CLK