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PCIe/PXIe-6301 Series |

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4.2.1

Channel Scan Sequence

The  scanning  order  of  the  channels  is  related  to  the  order  in  which  the  user  adds
channels.  When  the  acquisition  task  starts,  the  channels  added  by  the  user  will  be
assigned  to  each  ADC  according  to  the  group  to  which  they  belong.  Each  ADC  will
automatically  switch  channels  through  the  multiplexer  to  traverse  all  enabled
channels of the ADC for analog to digital conversion.

For a single ADC, the scan order is always consistent with the order in which the
channels within the ADC packet range are added. However, since the four ADCs work
at the same time, the scanning order of all the channels is not necessarily exactly the
same as the order in which the user adds the channels.

Figure 9 shows a typical channel scan sequence. In this case, the user added all
channels (Ch 0 ~ Ch 19) in order under the

“4

-

wire mdoe”

topology, and these

channels were automatically assigned to 4 ADCs. At the beginning of the acquisition
task, each ADC will start working at the same time, and then switch the channels in its
group.

ADC0

Ch0

Ch1

Ch2

Ch3

Ch4

Ch5

Ch18

Ch6

Ch7

Ch8

Ch9

Ch10

Ch11

Ch12

Ch13

Ch14

Ch15

Ch16

Ch17

Ch19

Ch5

Ch6

Ch7

Ch8

Ch9

Ch10

Ch11

Ch12

Ch13

Ch14

Ch18

Ch15

Ch16

Ch17

Ch19

Ch0

Ch1

Ch2

Ch3

Ch4

ADC1

ADC2

ADC3

Channels added by user

Ch0

Ch1

Ch2

Ch3

Ch4

Convert Sequence

time

Sample 0

Ch5

Ch6

Ch7

Ch8

Ch9

Ch10

Ch11

Ch12

Ch13

Ch14

Ch15

Ch16

Ch17

Ch18

Ch19

Figure 9 Typical channel scan sequence

Figure 10 shows another typical channel scan sequence, in which case the user added
some channels in random order under the

“4

-

wire mdoe”

topology.

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Содержание PCIe-6301 Series

Страница 1: ...PCIe PXIe 6301 Series 24 bits Temperature Input Module for Resistance Temperature Detector User Manual User Manual Version V2 1 3 Revision Date Aug 19 2021...

Страница 2: ...s 13 3 Software 17 System Requirements 17 System Software 17 C Programming Language 18 PCIe PXIe 6301 Hardware Driver 18 Install the SeeSharpTools from JYTEK 18 Running C Programs in Linux 18 4 Operat...

Страница 3: ...in Other Countries 55 JYTEK Hardware Products 55 JYTEK Software Platform 56 JYTEK Warranty and SupportServices 56 9 Statement 57 Figure 1 JYPEDIA Information 3 Figure 2 TB 68 terminal block 3 Figure 3...

Страница 4: ...re Level 3 46 Figure 32 Resistance Measurement noise 4 wire Level 4 47 Figure 33 Resistance Measurement noise 4 wire Level 5 47 Figure 34 Resistance Measurement noise 3 wire Level 0 48 Figure 35 Resis...

Страница 5: ...onfiguration supports 2 wire 3 wire or 4 wire RTD 14 Table 12 Pinouts for 3 wire mode configuration supports 2 wire 3 wire RTD 15 Table 13 Different RTD wiring methods 16 Table 14 Supported Linux Vers...

Страница 6: ...annel can support 2 wire or 3 wire RTD configuration and the module provides 32 channels of analog temperature measurements PCIe PXIe 6301 can measure resistance up to 400 to cover the full range of P...

Страница 7: ...ction Interface RTD Resistance Temperature Detector Ex Positive terminal of current Excitation Ex Ngative terminal of current Excitation RDC Resistance to Digital Converter OS Operating System 1 4 Lea...

Страница 8: ...easily relate the property names in the example program with the manual documentation In a Learn by Example section the experiment is set up as follow A PCIe PXIe 6301 card is plugged in a desktop com...

Страница 9: ...e time The wiring configuration used by each channel can be independently configured by software 2 wire RTD connection When using a 2 wire RTD configuration user needs to connect the negative terminal...

Страница 10: ...PCIe PXIe 6301 Series jytek com 5...

Страница 11: ...wn in Figure 4 Since the voltage generated by the RTD connecting the AI terminal and the voltage connected to the AI terminal will cancel each other this connection can effectively eliminate the influ...

Страница 12: ...ly so will not introduce errors due to lead wire resistance Figure 5 4 wire RTD connection 1 If you need to use a 4 wire configuration you must configure the channel topology to a 4 wire mode when con...

Страница 13: ...2 wire 3 wire 4 wire 20ch fully used 100 Sample s 2 wire 3 wire 32ch fully used Clock Onboard 25 MHz PX I_CLK100 Clock in PCIe TX I Only Storage depth 128M Samples Measuring range 0 400 200 850 for P...

Страница 14: ...iver software it corresponds to internal ADC conversion rate This information is important for you if you want to further improve the accuracy by averaging the acquired resistance values At level 0 AD...

Страница 15: ...ally do not use this information directly Table 5 Resistance Measurement noise Timing mode single conversion rate Single A D conversion time Noise 2 wire 3 wire RMS Noise 4 wire RMS Level 0 2 3 Hz 434...

Страница 16: ...red as output Table 7 PFI Specification Trigger Temperature Accuracy Levels Maximum Total Sample Rate S s 200 C 2 3 wires C 200 C 4 wires C 850 C 2 3 wires C 850 C 4 wires C Level 0 2 2 0 06 0 06 0 12...

Страница 17: ...e Clock source On Board Clock Destination Sample Clock Bus PXIe standard x4 PXI Express module specification rev 1 0 compliant Slot supported x1 and x4 PXI Express or PXI Express hybrid slots Size Ext...

Страница 18: ...Panel conections and Pinouts Figure 6 PXIe PCIe 6301 Front Panel PCIe PXIe 6301 supports two wiring topologies 4 wire mode and 3 wire mode The pinout of the 4 wire mode is shown in Table 11 the pinout...

Страница 19: ...ion only for 4 wire mode P58 Ex Positive terminal of current excitation only for 4 wire mode P49 AI resistance measurement high side P49 AI resistance measurement high side P15 AI resistance measureme...

Страница 20: ...sistance measurement high side P15 AI resistance measurement low side P15 AI resistance measurement low side P50 Ex Negative terminal of current exciation connet to AI for 2 wire configuration P50 Ex...

Страница 21: ...TD wiring methods RTD Type 2 wire 3 wire 4 wire 6301 Connection Connect AI AI Connect AI AI Ex Connect AI Ex AI Ex Short circuit AI and Ex Short circuit AI and Ex Short circuit AI and Ex Short circuit...

Страница 22: ...t website Microsoft Visual Studio Version 2015 or above NET Framework version is 4 0 or above NET Framework is coming with Windows 10 For Windows 7 please check NET Framework version and upgrade to 4...

Страница 23: ...e specific driver This driver provides rich and easy to use C interfaces for users to operate various PCIe PXIe 6301 functions JYTEK has standardized the ways JYTEK and other vendor s DAQ cards are us...

Страница 24: ...to run your C programs in Linux OS If you want to use your own Linux development system other than MonoDevelop you can do it using our Linux driver However JYTEK does not have the capability to suppo...

Страница 25: ...atform to operate the PCIe PXIe 6301 products If you are already familiar with Microsoft Visual Studio C the quickest way to use PCIe PXIe 6301 is to go through our extensive examples We provide sourc...

Страница 26: ...6301 Series jytek com 21 Figure 7 AI Continuous Paraments Click Start the result is shown below Figure 8 Single Channel Continuous Acquisition It shows that the temperature measured by channel0 is aro...

Страница 27: ...e order in which the user adds the channels Figure 9 shows a typical channel scan sequence In this case the user added all channels Ch 0 Ch 19 in order under the 4 wire mdoe topology and these channel...

Страница 28: ...es not necessarily match the order of adding channels the data is automatically reordered internally by the driver so the order of the data of each channel s reading data will always be the same as th...

Страница 29: ...6301 Series jytek com 24 Figure 11 AI MutilChannel Continuouas Paraments Click Start the result is shown below Figure 12 MultiChannel Continuous Acquisition It shows that the temperature measured by...

Страница 30: ...rive will automatically select the lowest possible rate level according to the sampling rate and the number of added channels If the user explicitly configures the rate level the driver will automatic...

Страница 31: ...ampling rate can be set according to the set rate grade and the number of channels added by each ADC for Max Total Sample Rate max number of channels on one ADC Where The maximum sample rate that can...

Страница 32: ...owing formula max number of channels on any one ADC Where Current actual total sampling rate max number of channels on any one ADC Maximum number of channels added on a single ADC User set sampling ra...

Страница 33: ...ernal conversion formula of the driver is referenced to the platinum RTD standard DIN IEC 60751 2008 Edition 2 0 ie When the temperature is between 200 C and 0 C Rt R0 1 At Bt2 C t 100 t3 When the tem...

Страница 34: ...any trigger condition setting by default Learn by Example 4 4 1 Connect the PT100 s positive pole to AI Pin 35 the negative poles to AI Pin 1 and Ex Pin 36 Open Winform AI Continuous Set parameters as...

Страница 35: ...digital trigger source and wait for the rising edge or falling edge of digital signal which depending on the set trigger condition then enables the module to acquire the data as shown in Figure 15 Ris...

Страница 36: ...Ie PXIe 6301 Series jytek com 31 Figure 16 Digital Trigger Paraments Trigger Source must match the pin on the terminal block There are two Trigger Conditions Rising and Falling The result is shown bel...

Страница 37: ...ek com 32 Figure 17 Digial Trigger Acquisition Since the squarewave is used for the digital trigger source when a rising edge of the squarewave occurs the digital trigger will be activated and the dat...

Страница 38: ...on task will start to acquire the signal immediately after the trigger asserted as shown in Figure 18 The Start Trigger mode is suitable for continuousand finite acquisition mode Sample Acquisition in...

Страница 39: ...PCIe PXIe 6301 Series jytek com 34 Figure 19 Start Trigger Paraments In Trigger Mode you can choose Start for Start Trigger Reference for Reference Trigger...

Страница 40: ...de The default number of pretrigger samples is 0 Example SamplesToAcquire 1000 PretriggerSamples 10 Posttrigger samples 990 1000 10 Sample Acquisition in Progress Sample Interval Trigger Pre Sample Po...

Страница 41: ...etrigger mode Learn by Example 4 5 2 and 4 5 3 Connect the PT100 s positive pole to AI Pin 35 the negative poles to AI Pin 1 and Ex Pin 36 then connect the signal source s positive pole and negative p...

Страница 42: ...er Samples is 10 Click Start to begin the data acquisition the result is shown below Figure 23 Retrigger in Reference Trigger Mode Because the measured waveform is a straight line the effect of refere...

Страница 43: ...ed as a bidirectional bus and it can synchronize up to four PCIe modules One PCIe module is designated as the master module and the other PCIe modules are designated as the slave modules Figure 25 SSI...

Страница 44: ...2 and 1 of the DIP switch to the ON position and the orthers to OFF See below for details Figure 26 DIP Switch in PCIe 6301 Table 18 Relationship between switch position and card number Position 4 GA3...

Страница 45: ...CIe PXIe 6301 boards are precalibrated before the shipment We recommend you recalibrate PCIe PXIe 6301 board periodically to ensure the measurement accuracy A commonly accepted practice is one year If...

Страница 46: ...ted in CPython version 3 5 There is no guarantee that JYTEK python drivers will work correctly with other versions of Python If you want to be our partner to support different Python platforms please...

Страница 47: ...The system is mainly composed of ADC DDR and FPGA control modules The FPGA based driver code provides a stable and efficient PCIe PXIe USB interface 6301 has four ADCs which can work alone or togethe...

Страница 48: ...PCIe PXIe 6301 Series jytek com 43 Appendix Table 1 PT100 Temperature Resistance Index Table...

Страница 49: ...PCIe PXIe 6301 Series jytek com 44 Appendix Table 2 PT100 Temperature Resistance Index Table continued from the previous table...

Страница 50: ...ance Measurement Noises Figure 28 Resistance Measurement noise 4 wire Level 0 Figure 29 Resistance Measurement noise 4 wire Level 1 0 6 0 4 0 2 0 0 2 0 4 0 6 0 100 200 300 400 500 600 700 800 900 1000...

Страница 51: ...PCIe PXIe 6301 Series jytek com 46 Figure 30 Resistance Measurement noise 4 wire Level 2 Figure 31 Resistance Measurement noise 4 wire Level 3...

Страница 52: ...PCIe PXIe 6301 Series jytek com 47 Figure 32 Resistance Measurement noise 4 wire Level 4 Figure 33 Resistance Measurement noise 4 wire Level 5...

Страница 53: ...PCIe PXIe 6301 Series jytek com 48 Figure 34 Resistance Measurement noise 3 wire Level 0 Figure 35 Resistance Measurement noise 3 wire Level 1...

Страница 54: ...PCIe PXIe 6301 Series jytek com 49 Figure 36 Resistance Measurement noise 3 wire Level 2 Figure 37 Resistance Measurement noise 3 wire Level 3...

Страница 55: ...8 Resistance Measurement noise 3 wire Level 4 Figure 39 Resistance Measurement noise 3 wire Level 5 Gain and Offset Stability Tests 30 20 10 0 10 20 30 0 100 200 300 400 500 600 700 800 900 1000 Ampli...

Страница 56: ...ure 40 Typical Drift 250 Input Figure 41 Typical Drift Different Inputs Reistance Measurement Error Tests are conducted to measure the resistance measurement errors The group axis represent each indiv...

Страница 57: ...PCIe PXIe 6301 Series jytek com 52 Figure 42 Typical Error 4 wire 100 Input Figure 43 Typical Error 4 wire 250 Input...

Страница 58: ...PCIe PXIe 6301 Series jytek com 53 Figure 44 Typical Error 3 wire 100 Input Figure 45 Typical Error 3 wire 250 Input...

Страница 59: ...PCIe PXIe 6301 Series jytek com 54 Figure 46 Typical Error 2 wire 100 Input Figure 47 Typical Error 2 wire 250 Input...

Страница 60: ...r have regular stocks to ensure timely supply we have R D centers in Xi an and Chongqing to develop new products we also have highly trained direct technical sales representatives in Shanghai Beijing...

Страница 61: ...our own developed hardware JYTEK also rebrands Adlink s PXI product lines In addition JYTEK has other rebranding agreements to increase our hardware coverage It is our goal to provide the complete pr...

Страница 62: ...ose or non infringement of intellectual property rights unless such disclaimer is legally invalid JYTEK is not responsible for any incidental or consequential damages related to performance or use of...

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