XV-M565BK/M567GD
1-59
Pin No.
Symbol
I/O
Function
ZIVA3-PEO (4/5)
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
3.3-V supply voltage for I/O signals.
Video data bus. Byte serial CbYCrY data synchronous with VCLK. At power-up,
the decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA
Ground for core logic and I/O signals.
Video data bus. Byte serial CbYCrY data synchronous with VCLK. At power-up,
the decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA
Programmable I/O pins. Input mode after reset.
Video data bus. Byte serial CbYCrY data synchronous with VCLK. At power-up,
the decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA
Programmable I/O pins. Input mode after reset.
Horizontal sync. The decoder begins outputting pixel data for a new horizontal line
after the falling (active) edge of HSYNC.
Vertical sync.Bi-directional, the decoder outputs the top border of a new field on the
first HSYNC aftre the falling edge of VSYNC. VSYNC can accept vertical
synchronization or top/bottom field notification from an external source.
(VSYNC HIGH = bottom field. VSYNC LOW = Top field)
Bistream data in IEC-1937 or PCM data out in IEC-958 format.
3.3-V supply voltage for I/O signals.
PCM data out, eight channels. Serial audio samples relative to DA-BCK clock.
Ground for core logic and I/O signals.
PCM data out, eight channels. Serial audio samples relative to DA-BCK clock.
PCM left-right clock. Identifies the channel for each audio sample. the polarity is
programmable.
PCM bit clock. Divided by 8 from DA-XCK can be either 48 or 32 times the sampling
clock.
2.5-V supply voltage for core logic.
Audio master frequency clock. Used to generate DA-BCK and DA-LRCK. DA-XCK can
be eigher 384 or 256 times the sampling frequency.
Ground for core logic and I/O signals.
PCM input data. two channels. Serial audio samples relative to DAI-BCK clock.
PCM input left-right clock.
PCM input bit clock.
Programmable I/O pins. Input mode after reset.
Clock Select: Internal = VDD, External = VSS
3.3-V analog supply voltage.
Video clock. Clocks out data on input. VDATA7.Clock is typically 27 MHz.
System clock.Decoder requires external 27 MHz TTL oscilator.
Drive with the same 27-MHz as VCK.
Analog ground for PLL
Serial CD data. This pin is shared with DVD compressed data DVD-DATA0.
3.3-V supply voltage for I/O signals.
Programmable polarity 16-bit word synchronization to the decoder
(right channel HIGH). This pin is shared with DVD compressed data DVD-DATA1.
Ground for core logic and I/O signals.
CD bit clock. Decoder accept multiple BCK rates. This pin is shared with DVD
compressed data DVD-DATA2.
Asserted HIGH indicates a corrupted byte.Decoder keeps the previous valid picture
on-screen unit the next valid picture is decoded. This pin is shares with DVD
compressed data DVD-DATA3.
-
O
-
O
I/O
O
I/O
I/O
I/O
O
-
O
-
O
O
O
-
I/O
-
I
I
I
I/O
I
-
I
I
-
I
-
I
-
I
I
E VDD
VDATA4
E VSS
VDATA5
TEST PIN7
VDATA6
VDATA7
TEST PIN8
HSYNC
VSYNC
IEC 958
E VDD
DA DATA0
E VSS
DA DATA1
DA DATA2
DA DATA3
DA LRCK
DA BCK
i vdd
DA XCK
i vss
DAI DATA
DAI LRCK
DAI BCK
TEST PIN9
CLK SEL
A vdd
VCLK
SYSCLK
A vss
DVD DATA0
E VDD
DVD DATA1
E-VSS
DVD DATA2
DVD DATA3
