JVC XV-M50BK, Руководство по обслуживанию

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XV-M52SL/XV-M50BK
1-35
Pin NO.
Symbol
I/O
Function
System control address
System control address
System control address
System control address
System control address
System control address
System control address
System control address
System control address
System control address
GND
System control address
System control chip select
System control write
System control read
Apply 3V
System control data
System control data
C=10000PF is connected between VSS
VSS connected
System control data
System control data
System control data
GND
System control data
System control data
System control data
16.9/11.2/8.45MHz clock
Apply 3V
Mirror gate
Data part frequency control switch
Part CAPA switch
RF dropout / BCA data of making to binary
Outer side CAPA detection
Side of surroundings on inside
GND
VSS connected
System reset
Apply 3V
16.9MHz clock
Frame mark detection
ID gate for tracking holding
Jump prohibition
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I
I/O
I/O
O
-
O
O
O
I
I
I
I
I
-
O
O
O
O
CPUADR10
CPUADR9
CPUADR8
CPUADR7
CPUADR6
CPUADR5
CPUADR4
CPUADR3
CPUADR2
CPUADR1
VSS
CPUADR0
NCS
NWR
NRD
VDD
CPUDT7
CPUDT6
PVPPDRAM
PTESTDRAM
PVDDDRAM
PVSSDRAM
CPUDT5
CPUDT4
CPUDT3
VSS
CPUDT2
CPUDT1
CPUDT0
CLKOUT1
VDD
TEHLD
DTRO
IDGT
BDO
CPDET2
CPDET1
VSS
MMOD
NRST
VDD
CLKOUT2
PLLOK
IDHOLD
JMPINH
MN103007BGA(2/4)