XL-R2010BK
1-22
Cereal
receive
circuit
Clock
generation
circuit
Display
controller
Display
control
register
Code/Command
control circuit
code select
Display code
register
(8bit 16)
Decoder
Decoder
CGROM
(35bit 160)
CGRAM
(35bit 16)
RAM write
Segment output circuit
Output port
(2bit)
Grid
output
circuit
14
19
60
23
31
33
59
17
18
15
16
13
21
20
22
32
FLCLKK
FLDAT
FLCS
RESET
XIN
XOUT
Vss
Vp
Vcc
Vcc2
P36
P28
1
12
12G
1G
61
64
16G
13G
P27
P01
P1
P0
1~12
13
14
15
16
17
18
19
20
21
22
23~31
32
33~59
60
61~64
12G~1G
SRST
FLCS
FLCLK
FLDATA
P1
P0
VCC1
XOUT
XIN
VSS
P36~P28
VP
P27~P01
VCC2
16G~13G
O
I
I
I
I
O
O
-
O
I
-
O
-
O
-
O
FL grid control signal output.
Reset signal input
Chip select signal input.
Shift clock signal input.
Serial data input.
Output port (static operation)
Output port (static operation)
Power supply for internal logic.
Clock signal output.
Clock signal input.
Connect to ground.
FL Segment control signal output.
Power supply.
FL Segment control signal output.
Power supply for grid output and segment output.
FL grid control signal output.
Pin.No.
Symbol
I/O
Description
1.Block diagram
2.Pin function
M66004FP-X(IC721):FL Driver