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1
20
21
40
41
60
61
80
12
4
5
12
2
11
2
SHI
Interface
Triple
Timer
ESAI
Interface
ESAI_1
Interface
GPIO
EFCOP
DAX
Peripheral
Expansion Area
PIO_EB
Address
Generation
Unit
Six Channel
DMA Unit
Bootstrap
ROM
Internal
Data
Bus
Switch
Clock
Gen-
erator
PLL
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
EXTAL
RESET
PINIT/NMI
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Data ALU
24 x 24+56 56-bit MAC
Two 56-bit Accumelators
56-bit Barrel Shifter
Power
Mngmnt.
JTAG
OnCE
TM
DDB
YDB
XDB
PDB
GDB
24-Bit
DSP56300
Core
DAB
YAB
XAB
PAB
PM_EB
YM_EB
XM_EB
Y Data
RAM
48K x 24
ROM
32K x 24
X Data
RAM
36K x 24
ROM
32K x 24
Program
RAM
4K x 24
ROM
64K x 24
Memory Expansion Area
DSPC56371AF180(IC2):DSP
1
FB
8 OUT
2
LBI
3
LBO
4
REF
7 LX
6 GND
5 SHDN
(Top View)
_MAINSWOFD
GND
V
DD
-
+
SENSEFET
-
+
V
DD
C
OUT
GND
V
DD
-
+
+
GND
-
+
+
CONTROL
LOGIC
_MAINSW2ON
_SYNSW2ON
Voltage
Reference
_SYNSWOFD
_ILIM
Chip
Enable
SHDN
REF
FB
_V
REFOK
_PFM
_CEN
_PWGONCE
_ZCUR
M1
LBO
LX
OUT
LBI
M2
GND
PFM
ZLC
ILIM
5
1
4
2
20 mV
R
SENSE
6
8
7
3
J47866-001(IC1):DC-DC Converter
LOGIC DIAGRAM
SERIAL
DATA
INPUT
14
11
10
12
13
SHIFT
CLOCK
RESET
LATCH
CLOCK
OUTPUT
ENABLE
SHIFT
REGISTER
LATCH
15
1
2
3
4
5
6
7
9
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
SQ
H
A
V
CC
= PIN 16
GND = PIN 8
PARALLEL
DATA
OUTPUTS
SERIAL
DATA
OUTPUT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
LATCH CLOCK
OUTPUT ENABLE
A
Q
A
V
CC
SQ
H
RESET
SHIFT CLOCK
Q
E
Q
D
Q
C
Q
B
GND
Q
H
Q
G
Q
F
J47872-001(IC11):LED Controller
2-7
2-8