JVC RX-6000VBK, Руководство по обслуживанию

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RX-6000VBK/RX-6008VBK/RX-6100VBK
2-10
No.
33
34
35
36
37
38
39
40
41
42
43
44
Negative voltage reference Input pin, AVSS
Common voltage output pin,AVDD/2
Large external capacitor around 2.2uF is used to reduce power-supply noise
Positive voltage reference input pin,AVDD
Analog power supply pin
Analog ground pin
X'tal input pin
X'tal output pin if XTS="H"
External master clock input pin if XTS="L"
Parallel/Serial select pin
"L" : Serial control mode, "H" : Parallel control mode
Audio data interface format pin in parallel mode
Chip select pin in serial mode
Audio data interface format pin in parallel mode
Control data clock pin in serial mode
Loop back mode pin in parallel mode
Enables digital loop-back from ADC to 3 DACs.
Control data input pin in serial mode
Loop back mode pin in parallel mode
Enable all 3 DAC channels to be input from SDTII.
Control data output pin in serial mode
Pin Name
VREFL
VCOM
VREFH
AVDD
AVSS
XTI
XTO
MCKI
P/S
DIF0
CS
DIF1
CCLK
LOOP0
CDTI
LOOP1
CDTO
Function I/O
I
O
I
-
-
I
O
I
I
I
I
I
I
I
I
I
O
AK4527(2/2)
3.Pin function
A0~A16
I/O1~I/O8
CS
WE
OE
Vdd
Vss
Address inputs
Data inputs/outputs
Chip select inputs
Write enable input
Output enable input
Power supply
Ground
Symbol Description
A0
A1
A2
A3
CS
I/O1
I/O2
VDD
VSS
I/O3
I/O4
WE
A4
A5
A6
A7
A16
A15
A14
A13
OE
I/O8
I/O7
VSS
VDD
I/O6
I/O5
A12
A11
A10
A9
A8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vdd
Vss
A0
A16
CS
OE
WE
I/O1
I/O8
DECODER
CORE
ARRAY
CONTROL
DATA I/O
M24L011AJ-15(IC641):SDRAM
1.Pin layout 2.Block diagram 3.Pin function