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MX-K35V
1-26
ES3883F (IC102) : Companion chip
1. Terminal layout
2. Pin function
Symbol
I/O
Pin No.
Symbol
I/O
Function
1
2~4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25,26
27~30
31
32
33
34
35
36
37
38
39
40
41
42
43
VSS
NC
VCC
DSC_C
AUX0
DSC_D0
AUX1
DSC_S
AUX2
DCLK
EXT_CLK
RESET_B
AUX7/NFD_DI
MUTE
VCC
MCLK
AUX8/NFD_CLK
TWS
SPLL_OUT
AUX9/SQSO
TSD
TBCK
RWS
SEL_PLL1
RSTOUT_B
VSS
NC
VSS
VCC
RSD
SEL_PLL0
AUX10/SQCK
AUX11/IRQ
AUX12/C2PO
RBCK
SER_IN
AUX13/SP
AUX14/SOSI
AUX15/IR
VSSAA
VCM
VREFP
Ground
No connect
Voltage supply, 5V
Clock for programming to access internal
registers
Servo forward or general-purpose I/O
Data for programming to access internal
registers
Servo reverse or general-purpose I/O
Strobe for programming to access internal
registers
Servo LDON or general-purpose I/O
DCLK is the MPEG decoder clock.
EXT_CLK is the external clock.
EXT_CLK is an input during bypass PLL mode.
Video reset (active-low)
Servo BRKM/sense or general-purpose I/O / VFD_DI
Audio mute
Voltage supply, 5V
Audio master clock
Servo mute/open or general-purpose I/O / VFD_CLK
TWS is the transmit audio frame sync.
SPLL_OUT is the select PLL output.
Servo SQSO or general-purpose I/O
Transmit audio data input
Transmit audio bit clock
RWS is the receive audio frame sync.
SEL_PLL[1:0] select the PLL clock frequency for
the DCLK output.
SEL_PLL1
SEL_PLL0
DCLK
0
0
Bypass PLL (input mode)
0
1
27MHz (output mode)
1
0
32.4MHz (output mode)
1
1
40.5MHz (output mode)
Reset output (active-low)
Ground
No connect
Ground
Voltage supply, 5V
RSD is the receive audio data input.
SEL_PLL0 and SEL_PLL1 select the PLL clock
frequency for the DCLK output. Refer to the
table in the definition for pin 23.
Servo SQCK or general-purpose I/O
ES3880 IRQ or interrupt output or general-purpose I/O
CD C2PO or interrupt input or general-purpose I/O
RBCK is the receive audio bit clock.
SER_IN is the serial input DSC mode:
0 = Parallel DSC mode
1 = Serial DSC mode
Serial interrupt/CD-mute or general-purpose I/O
Servo SCOR (SOSI), interrupt input,
or general-purpose I/O
Interrupt input or general-purpose I/O
Audio analog ground
ADC common mode reference (CMR) buffer output.
CMR is approximately 2.25V. Bypass to analog ground
with 47uF electrolytic in paralell with 0.1uF.
DAC and ADC maximum reference. Bypass to video
CMR (VCMR) with 10uF in parallel with 0.1uF.
-
-
-
I
I/O
I/O
I/O
I
I/O
O
I
I
I/O
O
-
I
I/O
I
O
I/O
I
I
O
I
O
-
-
-
-
O
I
I/O
I/O
I/O
O
I
I/O
I/O
I/O
-
I
I
80 ~ 51
1 ~ 30
100 ~ 81
31 ~ 50
44
45,46
47,48
49
50
51
52
53
54
55
56,57
58
59,60
61
62,63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86~89
90
91
92
93
94
95
96
97
98
99
100
VCCAA
AOR+,AOR-
AOL-,AOL+
MIC1
MIC2
VSSAA
VREF
VREFM
RSET
COMP
VSSAV
CDAC
VCCAV
YDAC
VSSAV
VDAC
ACAP
VCC
AUX6/VFD_DO
AUX5
AUX4
AUX3
XOUT
VSS
VCC
XIN
VSS
NC
VSS
VCC
PCLK
2XPCLK
DSC_D7
HSYNC_B
DSC_D6
VSYNC_B
DSC_D5
YUV7~4
VCC
VSS
YUV3
DSC_D4
YUV2
DSC_D3
YUV1
DSC_D2
YUV0
DSC_D1
VSS
Analog VCC, 5V
Right channel output
Left channel output
Microphone input 1
Microphone input 2
Audio analog ground
Internal resister divider generates CMR
voltage.
Bypass to analog ground with 0.1uF.
DAC and ADC minimum reference.
Bypass to VCMR with 10uF in parallel
with 0.1uF.
Full-scale DAC current adjustment
Compensation pin
Video analog ground
Modulated chrominance output
Video VCC, 5V
Y luminance data bus for screen video
port
Video analog ground
Composite video output
Audio CAP
Voltage supply, 5V
Servo XLAT or general-purpose I/O / VFD_DO
Servo data or general-purpose I/O
Servo CCW/close or general-purpose I/O
Servo CW/limit or general-purpose I/O
Crystal output
Ground
Voltage supply, 5V
27MHz crystal input
Ground
No connect
Ground
Voltage supply, 5V
13.5MHz pixel clock
27MHz(2 times pixel clock)
Data for programming to access internal
registers
Horizontal sync (active-low)
Data for programming to access internal
registers
Vertical sync (active-low)
Data for programming to access internal
registers
YUV data bus for screen video port
Voltage supply, 5V
Ground
YUV data bus for screen video port
Data for programming to access internal
registers
YUV data bus for screen video port
Data for programming to access internal
registers
YUV data bus for screen video port
Data for programming to access internal
registers
YUV data bus for screen video port
Data for programming to access internal
registers
Ground
I
O
O
I
I
-
I
I
I
I
-
O
-
O
-
O
I
-
I/O
I/O
I/O
I/O
O
-
-
I
-
-
-
-
I/O
I/O
I/O
O
I/O
O
I/O
I
-
-
I
I/O
I
I/O
I
I/O
I
I/O
-
Pin No.
Function