No. YA099
No. YA099
2-39
2-40
: NRSA63J-0R0X
: NRZ0034-0R0W
RA0
0
NOTE
BS_RXD
D7601
MI_SW
RA7602
C7618
X7601
R7688
R7657
R7661
R7658
R7686
R7656
C7607
C7608
C7609
C7610
C7611
R7659
R7660
C7612
R7681
C7622
REMO
R7685
KEY1
OSDB5
C7613
OSDB4
OSDB3
OSDG5
OSDG4
OSDG3
OSDR5
OSDR4
OSDR3
R7680
KEY2
PW/CLK
RESET
WORD/TXD
C7619
SCLM
SDAM
CARD_DET
WAKE
C7621
SBD5
SBT5/RTS
DD_OSDHS
R7690
RB7614
R7689
RB7615
DD_OSDVS
IC7607
R7606
R7608
R7609
DD_OSDCK
R7615
SUB_CCD1
MAIN_CCD
MI_OSDYS
IC7603
R7691
C7615
C7614
C7603
IC7602
C7616
R7607
IC7608
MI_OSDYM
MI_REQ
MI_CK
MI_TX
MI_RX
ACINPOW
RB7605
TVLINK
R7611
R7613
R7614
R7610
R7612
BS_TXD
RA7601
RA7603
RA7604
RA7605
MECA_SW
CN0MM
R7692
Tx5057
Rx5057
C7606
C7605
R7666
R7603
R7605
R7602
R7663
C7617
R7664
R7604
R7601
C7602
C7601
P4.4
P4.5
P4.6
P4.7
WR
P5.1
P5.2
P5.3
P5.4
HOLD
P5.6
P5.7
RTS0
CLK0
RxD0
TxD0
DIGB1
DIGG1
DIGR1
SDA2
DIGR2
DIGG2
DIGB2
VHOLD2
HLF2
CVIN2
TVSETB
VCCE
CVIN1
POWER_SW
KEY2
KEY1
CARD_DET
WAKE
CB1
CB2
CF1
CF1
CB1
NC
A
GND
Vcc
Y
/10
CB1
VCC3D
Tx5057
Rx5057
GND
BS_RXD
BS_TXD
QGA1501F2-06V
VHOLD1
HFLT1
DIGR0
BYTE
CNVss
DIGG0
DIGB0
RESET
Xout
Vss
Xin
Vccl
OSC1
OSC2
OUT1
OUT2
CTA2/RTS2
CLK2
RxD2
TxD2
VSYNC
HSYNC
INT0
INT1
TB1in
REMO
CH
CH
SAG
OUT
Vcc
PS
GND
IN
CH
CB2
Vcc
TEST
SCL1
SDA1
A0
A1
A2
Vss
SAG
OUT
Vcc
PS
GND
IN
CH
*4
RA0
10/10
0
0
470
1k
1M
0
1000p
220p
2.2/10
680p
680p
6.8k
1M
0.1
0
4.7/16
470
0.1
0
4.7/16
10/10
0
0
0
0
0
2.2k
3.3k
0
33k
0.1u
0.1u
2.2u
1/16
0
0
0
2.2k
3.3k
0
0
RA0
RA0
RA0
RA0
15p
15p
0
10k
0
10k
OPEN
0.1
1k
0
1k
220p
1000p
SBD5
DD_OSDHS
PW/CLK
DD_OSDVS
WORD/TXD
DD_OSDVS
MECA_SW
OSDCK_IN
SUBCCD
MI_OSDYS
MI_OSDYM
MAINCCD
DGND
DGND
VCC3D
BS_TXD
MI_TX
BS_RXD
DD_OSDHS
DGND
OSDR5
OSDG5
ACINPOW
TVLINK
OSDB5
WAKE
OSDG4
PW/CLK
OSDR4
OSDB4
KEY2
KEY1
SUBCCD
DGND
DGND
OSDR5
MI_CK
MI_RX
OSDR4
OSDR3
WORD/TXD
RESET
STB3.3V
BS_5V
AGND
SBD5
MI_SW
OSDG3
OSDG4
OSDG5
OSDB3
OSDB4
OSDB5
REMO
KEY1
KEY2
AGND
STB3.3V
DGND
DGND
STB_5V
MI_SW
BS_RXD
BS_TXD
SBT5/RTS
SBT5/RTS
MI_REQ
MI_CK
MI_TX
MI_RX
MAINCCD
AGND
BS_5V
AGND
BS_TXD
RESET
MECA_SW
OSDCK_IN
BS_RXD
MI_OSDYS
MI_OSDYM
OSDR3
OSDG3
OSDB3
REMO
ACINPOW
MI_REQ
TVLINK
NOTES) 1. Please refer to page 2-90 for voltages of this circuit diagram.
2. Please refer to page 2-92 for waveforms of this circuit diagram.
SHEET17
SHEET11
SHEET17,18
SHEET13
OPEN
DIGITAL SIGNAL PWB ASS'Y (9/11)
SFP0D503A-M2 [PD-42V475/S]
SFP0D504A-M2 [PD-42V485/S]
OPEN
MAIN CPU
SHEET13
SHEET15
SHEET11
SHEET17
SHEET10
SHEET17
SHEET17
SHEET15
IC7601
M306V7MG-091FP
MAIN MEMORY
AT24C32-42V485
DIGITAL SIGNAL PWB CIRCUIT DIAGRAM (9/11) SHEET16
Содержание I'Art Palette PD-42V475
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