2-21(No.YF133)
IC44
JCY0
[Standa
IC4403
MM3142FN-X
[2.5V_REG]
VCLK
1
GND
2
GND
6
GND
9
VDD
13
GND
14
VDD
98
VDDI
15
NC
24
GND
26
NC
27
GND
28
GND
30
VDD
39
GND
40
VDD
41
NC
42
GND
43
GND
47
GND
102
GND
86
GND
103
GND
104
GND
105
GND
107
GND
90
TMS
44
TRST
45
TDO
121
GND
122
GND
123
VDD
124
GND
125
GND
126
GND
127
GND
66 DIN9
16 DIN10
65 DIN11
71 SOFI
22 VPIXI
128 VDD
130 AGND
131 AVDD
132 GND
133 GND
10 SDT
11 SEN
12 SCK
134 GND
135 GND
136 NC
137 GND
138 GND
139 GND
141 GND
142 GND
144 GND
145 VDD
146 GND
147 GND
157 VDDI
148 GND
149 GND
21 DIN0
70 DIN1
20 DIN2
69 DIN3
19 DIN4
68 DIN5
18 DIN6
67 DIN7
17 DIN8
7
CLR
8
TVSEL
156
GND
158 GND
159 GND
160 GND
IC4402
OPEN
8
CLK/2
7
CLK
6
S0
5
FBIN
4
ICLK
3
GND
2
VDD
1
S1
C4401
4.7/6.3
L4401
NQR0006-001X
SOF
PPRO3
PPRO7
PPRO1
PPRO5
PPRO10
PPRO9
PPRO0
PPRO2
PPRO8
PPRO6
VLD_PIX
PPRO4
VCLK
PPRO11
C4404
0.1
C4406
0.1
C4408
OPEN
AFE_RST
TVSEL
R4420
OPEN
R4419
OPEN
GA_SDT
GA_CS
GA_SCK
C4
0.1
REG_3.1V
GND
C4409
OPEN
R4418
47
161
GND
R4421
OPEN
R4422
C4411
1
R4417
OPEN
1
VDD
2
GND
3
CE
4
NC
5
VOUT
C4412
1
L4402
NQR0006-001X
C4407
4.7/6.3
0
Ω
[JCY0227:GND]
[JCY0227:GND]
[JCY0227:VDD]
[JCY0227:VDD]
[JCY0227:VDD]
[JCY0227:GND]
[JCY0227:GND]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:NC]
[JCY0227:GND]
[JCY0227:NC]
[JCY0227:NC]
TO SUB CPU,P.PRCS
TO P.PRCS
MAIN(GA) SCHEMATIC DIAGRAM
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.