2-15(No.YF098)
IC40
R4048
R4068
R4081
R4007
RA4005
RA4006
R4076
DSP_RSV
C4044
SSGFLD
CCD_CTL
R4029
NDPWM
STRB_ENV
CLK27A
R4001
R4069
R4061
R4008
X4001
C4043
R4024
nPMCS1
R4016
TL4018
PPRO0
PPRO1
PPRO2
PPRO3
PPRO4
PPRO5
PPRO6
PPRO7
PPRO8
R4017
PPRO9
SDR_CKE
SDR_BA0
SDR_BA1
SDR_CS0
SDR_RAS
SDR_CAS
SDR_WE
SDR_DQM0
SDR_DQM1
SDR_DQM2
SDR_DQM3
SDR_DQ0
SDR_DQ1
SDR_DQ2
SDR_DQ3
SDR_DQ4
SDR_DQ5
SDR_DQ6
SDR_DQ7
SDR_DQ8
SDR_DQ9
SDR_DQ10
SDR_DQ11
SDR_DQ12
SDR_DQ13
SDR_DQ14
SDR_DQ15
SDR_DQ16
SDR_DQ17
SDR_DQ18
SDR_DQ19
SDR_DQ20
SDR_DQ21
SDR_DQ22
SDR_DQ23
SDR_DQ24
SDR_DQ25
SDR_DQ26
SDR_DQ27
SDR_CLK
SDR_A10
SDR_A9
SDR_A8
SDR_A7
SDR_A6
SDR_A5
SDR_A4
SDR_A3
SDR_A2
SDR
A1
SDR_DQ28
SDR_DQ29
SDR_DQ30
SDR_DQ31
R4056
PMINT
PPRO10
PPRO11
V1CLK
VLD_PIX
SOF
AFE_RST
R4025
R4027
R4013
V2CLK
R4026
TL4014
TL4015
TL4016
nARMTRST
nPMCS7
ARMTCK
ARMTMS
ARMTDI
ARMTDO
PMD15
PMD14
PMD13
PMD12
PMD11
PMD10
PMD9
PMD8
PMD7
PMD6
PMD5
PMD4
PMD3
PMD2
PMD1
PMD0
nPMBLS0
PMA20
PMA19
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMA11
PMA12
PMA13
PMA14
PMA15
PMA16
PMA17
PMA18
PMA2
PMA1
PMA0
NC(TL4098)
R4023
R4058
nPMWE
nPMOE
nPMBLS1
R4002
C4022
ID_LAT
DSP_RST
TL4001
R4005
nPMWAIT
DMACLR
DMABREQ
R4009
R4010
PMA21
TL4027
MOD0
VDCPU
L4007
DMASREQ
TL4026
R4022
R4020
nJRESET
R4055
R4021
R4006
R4019
R4018
R4015
R4014
R4012
R4011
TL4002
TL4003
GPIO7
GPIO26
GPIO28
GPIO25
GPIO27
PWM0
PWM1
PWM2
PWM3
NC3
NC4
GPIO39
GPIO31
CFWP
nCFWE
nCFWAIT
CFRESET
nCFREG
nCFOE
nCFIOWR
nCFIORD
CFCSEL
CFD0
CFD1
CFD2
CFD3
CFD4
CFD5
CFD6
CFD7
CFD8
CFD9
CFD10
CFD11
CFD12
CFD13
CFD14
CFD15
nCFCE0
nCFCE1
nCFCD1
nCFCD2
CFBVD1
CFBVD2
CFA0
CFA1
CFA2
CFA3
CFA4
CFA5
CFA6
CFA7
CFA8
CFA9
CFA10
CFRDY
SIP1280I
NAX0392-0
MCLKIN
NC
AMBACLKIN
nRESET
SCANE
TESTSCAN
TRACESYNC
TRACECLK
DBGRQ
DBQACK
PMA0
nPMCS7
nPMCS1
nPMCS0
nPMWE
nPMOE
nPMBLS0
nPMBLS1
nPMWAIT
SDRAM_A8
SDRAM_A9
SDRAM_A10
SDRAM_A11
SDRAM_A12
SDRAMCLK
SDRAMCLKR
SDRAMBS0
SDRAMBS1
nMCS0
nRAS
nCAS
nMWE
DQM0
DQM1
DQM2
DQM3
MCKE
AFED0
AFED1
AFED2
AFED3
AFED4
AFED5
AFED6
AFED7
AFED8
AFED9
AFED10
AFED11
AFECLK
3CCDCLK
AFEVPIX
AFESOF
GPIO6
nARMTRST
TCK
TMS
TDI
AMBATDO
GPIO2
GPIO3
GPIO5
GPIO4
SDRAM_D0
SDRAM_D1
SDRAM_D2
SDRAM_D3
SDRAM_D4
SDRAM_D5
SDRAM_D6
SDRAM_D7
SDRAM_D8
SDRAM_D9
SDRAM_D10
SDRAM_D11
SDRAM_D12
SDRAM_D13
SDRAM_D14
SDRAM_D15
SDRAM_D16
SDRAM_D17
SDRAM_D18
SDRAM_D19
SDRAM_D20
SDRAM_D21
SDRAM_D22
SDRAM_D23
SDRAM_D24
SDRAM_D25
SDRAM_D26
SDRAM_D27
SDRAM_D28
SDRAM_D29
SDRAM_D30
SDRAM_D31
PMA1
PMA2
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMA11
PMA12
PMA13
PMA14
PMA15
PMA16
PMA17
PMA18
PMA19
PMA20
PMA21
PMD0
PMD1
PMD2
PMD3
PMD4
PMD5
PMD6
PMD7
PMD8
PMD9
PMD10
PMD11
PMD12
PMD13
PMD14
PMD15
nRESETPERH
DMASREQ
DMACLR
DMABREQ
GPIO24
SIO1
SIO0
SDRAM_A7
SDRAM
A6
USBPHYCLK
NQR0006-001X
0
Ω
47k
47k
10k
47k
47k
47k
0.1
0
Ω
100
1k
47k
0.1
0
Ω
0
Ω
0
Ω
100
47k
0
Ω
0
Ω
0
Ω
47k
0
Ω
3.3k
47k
47k
47k
47k
180
47k
0
Ω
0
Ω
0
Ω
0
Ω
0
Ω
0
Ω
0
Ω
SDR_CLK
SDR_A6
SDR_A7
SDR_CS0
SDR_BA1
SDR_BA0
SDR_DQM3
SDR_DQM2
SDR_DQM1
SDR_DQ31
SDR_DQ30
SDR_DQ29
SDR_DQ28
SDR_DQ27
SDR_DQ26
SDR_DQ25
SDR_DQ24
SDR_DQ23
SDR_DQ22
SDR_DQ21
SDR_DQ20
SDR_DQ19
SDR_DQ18
SDR_DQ17
SDR_DQ16
SDR_DQ15
SDR_DQ14
SDR_DQ13
SDR_DQ12
SDR_DQ11
SDR_DQ10
SDR_DQ9
SDR_DQ8
SDR_DQ7
SDR_DQ6
SDR_DQ5
SDR_DQ4
SDR_DQ3
SDR_DQ2
SDR_DQ1
SDR_DQ0
SDR_DQM0
SDR_WE
SDR_CAS
SDR_RAS
SDR_CS0
SDR_BA1
SDR_BA0
SDR_CKE
SDR_CLK
SDR_A10
SDR_A9
SDR_A8
SDR_A7
SDR_A6
SDR_A5
SDR_A4
SDR_A3
SDR_A2
SDR_A1
SDR_A8
SDR_A9
SDR_A10
SDR_A11
SDR_A12
SDR_RAS
SDR_CAS
SDR_WE
SDR_DQM0
SDR_DQM1
SDR_DQM2
SDR_DQM3
SDR_DQ0
SDR_DQ1
SDR_DQ2
SDR_DQ3
SDR_DQ4
SDR_DQ5
SDR_DQ6
SDR_DQ7
SDR_DQ8
SDR_DQ9
SDR_DQ10
SDR_DQ11
SDR_DQ12
SDR_DQ13
SDR_DQ14
SDR_DQ15
SDR_DQ16
SDR_DQ17
SDR_DQ18
SDR_DQ19
SDR_DQ20
SDR_DQ21
SDR_DQ22
SDR_DQ23
SDR_DQ24
SDR_DQ25
SDR_DQ26
SDR_DQ27
SDR_DQ28
SDR_DQ29
SDR_DQ30
SDR_DQ31
SDR_CKE
TO P.PRCS
TO P.PRCS
TO MEMORY
P.PRCS
TO P.PRCS
TO SYSCON
P.PRCS
TO JIG CONN
(CN110)
TO P.PRCS
TO
P.PRCS
TO MEMORY
TO SYSCON
TO SYSCON
P.PRCS
TO SYSCON
TO P.PRCS
TO OP DRV
TO MAIN IF(CN103)
TO MAIN IF(CN101)
TO JIG CONN
(CN110)
TO MEMORY
P.PRCS
TO MEMORY
P.PRCS
TO P.PRCS
TO
JIG CONN
(CN110)
TO MEMORY
TO MEMORY
TO P.PRCS
MAIN(NUCORE) SCHEMATIC DIAGRAM
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.