2-17(No.YF076)
CH
C4914
68p
VDIRS
DUMP_CTL
PBVCOCTL
IRIS_CS
M_REG4.8
C4910
OPEN
R4918
10k
T_F_V_RST
HDIRS
R4901
24k
C4951
OPEN
R4910
100
15k
R4905
R4909
1M
L4954
NQL38DK-100X
10u
C4921 0.01
R4923
12k
R4904
10k
T_F_V_RST
L4901
NQR0129-002X
R4902
10k
CAM_OUT
R4908
4.7k
R4907
1M
R4912
100
T
C4952
10/6.3
C4953
OPEN
REG_4.8V
CH
C4911
OPEN
C4907
0.1
L4953
NQR0129-002X
F/Z_MCK
R4945
10k
REC_ADJ
C4909
0.01
C4920
OPEN
R4944
C4922 0.1
C
0
C4906
0.1
L4902
NQL38DK-100X
10u
IC4901
JCY0215-X
1
2
11
54
12
13
22
63
23
24
33
72
34
35
44
45
T
C4954
10/6.3
CH
C4915
120p
VOI_IN
L4955
NQL38DK-100X
10u
ASPECT
FSPLLCTL
CAM_CLK
REG_3.1V
T
C4902
10/6.3
T
C4956
10/6.3
OPEN
R4903
8.2k
R4911
100
T
C4904
10/6.3
VD_F/Z
C4913
0.1
IRIS_PS
IR_OUT
M_VCOCTL
R4935
100k
VOI_OUT
NOSIG_LV
ATF_GAIN
GND
VOI_CLK
LENS_LED
C4916
0.1
R4906
680k
IRIS_MCK
C4955
OPEN
C4918 0.1
F/Z_CS
R4917
10k
R
C4908
0.1
IC4901
JCY0215-X
46
3
47
4
48
5
49
6
7
50
8
51
9
52
10
53
55
14
56
15
57
16
58
17
18
59
19
60
20
61
21
62
64
25
65
26
66
27
67
28
29
68
30
69
31
70
32
71
73
36
74
37
75
38
76
39
40
77
41
78
42
79
43
80
C4905
0.1
C4917
0.1
TL4904
TL4948
TL4905
TL4949
TL4906
TL4907
TL4950
TL4908
TL4951
0
Ω
MAIN(OP DRV)
1
0
TO CPU
VIDEO
TO CPU
TO CPU,
CDS/TG
TO CPU,
MAIN IF(CN103)
TO MAIN IF
(CN104)
TO PARAGON
TO VIDEO
TO CPU
TO REG
TO CPU,
CDS/TG
TO CPU,
CDS/TG
TO PARAGON
TO PARAGON
TO PARAGON
TO CPU
MAIN(OP DRV) SCHEMATIC DIAGRAM
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.