5
4
3
2
1
A
B
C
D
E
F
G
2-81
2-82
*1
TO
PHYXTPA
16
20
IC8001
156
82
PHYTPB
PHYTPA
226
286
PHYXTPB
185
109
108
AIMCK
AIBCK
AILRCK
TPB-
TPA-
TPB+
TPA+
AIDAT
AODAT
AILRCK
AIBCK
246
AIDAT1
AODAT0
AIMCK
AIDAT0
248
112
OSC27I
CPUWAIT
XCPURW
XCPUDSTB1
XCPUDSTB0
CPUALE
BRSO0
BRSO3
142
CDALE
DV_WATT
66
DRWSEL
213
143
212
150
67
DV_RST
ADDT15
ADDTO0
AD0
64
AD15
XRESET
CLK27A
38
119
39
INV
INH
43
122
OUTH
OUTV
MAIN
0
1
257
193
194
258
YSO3
YSO0
242
IEE1394
LINK
( ISO/
ASYNC
FIFO )
D-RAM I/F
HOST CPU I/F
(DECK_DSP)
AUDIO
( WORK RAM
PROGRAM
RISC CORE )
( CLOCK CONV )
RAM
SPA
HSP
HID
TRKREF
FRREF
98
101
243
240
TSR
FRP
RAM
( SUB/AUX )
IC3001
(DVMAIN)
( VBID DET RAM )
VIDEO I/F
( ENC/DET )
COMPRESS
( DCT,VLC VLD
WORK RAM )
OUTER ECC
FORMATTER
( Formatting Sync
Detect ID Protect
De-formatting )
(ENC/DEC)
PWMAUDIO
RECDATA
RECCTL
RECCLK
173
174
100
182
AUDIO_CS
S_SHUT
PD_L
DV IN/OUT
TPB+
TPB-
TPA-
DV
TPA+
TO IC3001
AIDAT
AODAT
AIBCK
AILRCK
AIMCK
AUDIO
TO
AUDIO
TO
TO IC1001,IC8001
DOLRCK2
DOBCK2
AIDAT2
AU,DA
TO
SPA
REC_CTL
REC_CLK
FSPLLCTL
DAAOUT0
DAAOUT1
DISCRI
OSC27I
OSC27O
PWM27O
11
237
106
IC3005
AMP+
AMP-
AMPO
4
1
2
A0~A19
DQ0~DQ15
IC8003
( 16M_FLASH RAM )
9
45
25
29
DSC R/D_DATA
DSC R/D_ADRESS
39
108
7
20
HDDSC
CLKDSC
DSYO7
DSCO0
VDDSC
DSC_WKUP
DSC_CS
FLSH_RST
DSC_CLK
DSC_DT_OUT
DSC_DT_IN
USBDOWN
DSC_RST
MXDT_OUT
CAPT_REQ
DSC_STS
DSYO0
DSCO7
DSCIO0
DSCIO7
DSYIO7
DSYIO0
176
246
244
188
247
191
190
237
235
172
249
199
FLDDSC
212
AIDAT2
94
239
157
125
206
184
135
205
182
136
138
IC8004
TO
IC8003-12PIN
1
2
YIO0
YIO7
CIO0
CIO7
YIN0
YIN7
CIN0
CIN7
CLKIN1
HDIN
VDIN
FID
MXI
MXO
GIO0
GIO18
SCLK1
SDI1
26
28
11
12
FLSH_CE
FLSH_OE
FLSH_WE
RESET
SDO1
GIO13
RESET
GIO12
GIO7
GIO11
FROM
RAS
WE
CS
CAS
CKE
CLK
A0
2
DQ0
15
159
51
2
3
49
30
177
201
160
195
193
180
SDRAM_DATA
SDRAM_ADRESS
IC8002
CXO
X8002
48MHz
2
MMC_CLK
5
7
9
174
173
250
117
SDI3
SCK3
SDO3
GIO20
ARM_D15
ARM_D0
ARM_A19
ARM_A0
EM_CSO
EM_OE
EM_WE
M48XI
M48XO
SDR_DQ0
SDR_A0
SDR_CKE
SDR_CLK
SDR_CS
SDR_CAS
SDR_DQMLH
SDR_RAS
SDR_WE
SDR_DQMLL
DSC
MMC_DC
164
GIO2
GIO15
128
GIO15
GIO6
147
GIO6
GIO3
1158
GIO3
11
85
9
D8001
R8068
R3034
R3010
R3009
C3024
M_VCOCTL
L3007
C3023
R3011
D3001
23
104
105
24
(PRE/REC)
48
AGC_BUFF_OUT
10
REC_GAIN
57
PB_MONI
12
44
7
MONI_CHG
R_CTL
REC_DATA
9
REC_CLK
Y1
19
X2
25
X1
20
HID3
40
42
41
HID1
REC_H
PB_H
38
Y2
24
IC3501
2
4
IC3502
HEAD
2
1F
7
3
6
2S
1S
2F
b
a
c
TO
CAMERA DSP
TO
CAMERA DSP
d
TO
CPU
TO
CAMERA DSP
CDDSTB
CDWE
CLK27SEL
CPU
HID1
AO5
FSPLLCTL
RECCADJ
ATF_GAIN
4
18
19
5
AO1
AO2
AO6
IC3002
(DVMAIN)
VIFD_OUT
VIFD_CLK
17
DI
CLK
16
ADVIN0
AGC_OUT
168
J501
AU_DATA
AU_CLK
BUZZER
L_MOTE
A_MOTE
TO
MONI
㧙
C
CN103
MMC_DATA
M32_MMC_CS
MMC_CMD
IC1001-6PIN
146
SDR_DQ31
C8026
R8022
TO
CPU
TO
CAMERA DSP
CLK27B
64M
SDRAM
DQMO
DQM1
A14
DQ31
19
200
17
16
178
28
20
18
71
67
68
25
24
56
149
129
122
ENV_OUT
RECCADJ
AGC_OUT
MONI_CHG
REC_DATA
REC_CTL
REC_CLK
HID1
RECH
PBH
HID3
ENV_OUT
RECCADJ
AGC_OUT
ATF_GAIN
ATF_GAIN
MONI_CHG
REC_DATA
REC_CTL
REC_CLK
HID1
RECH
PBH
HID3
TO
CPU
TO
JIG CONN
(CN105)
3
5
6
4
25
7
33
8
11
14
22
23
38
36
35
37
20
34
8
33
30
27
19
18
CN110
CN401
60
PRE/MDA
0
5
CN402
SDR_A14
TO CPU
*1 WITH DSC MODEL
INNER ECC
( CLOCK CONV )
RAM
( CLOCK CONV )
RAM
( CLOCK CONV )
RAM
239
BUFF
Q3002
VCI4185
REC_DATA
AO11
AO12
H_GAIN
H_OFFSET
12
13
TO
OP-DRV
ATF_GAIN
DOMCK2
PWAD2
*1
CN112
1
V_OUT
REAR UNIT ASS'Y
VOUT
12
TO
IC1001
TO IC4301
TO
JIG CONN
CN105
PS_PLL
16
D0
㧙
D15
TO USB
28
EM_CS2
EM_CS2
FLSH_OE
FLSH_WE
A10
3
CN762
SDR_DQMHL
DQM2
59
DEM3
SDR_DQMHH
TO
J502
USBSENS
CLKIN2
219
DSP_BDR
114
104
105
DSP_BFSR
DSP_BFSX
DSP_BCLKR
DSP_BCLKX
DOLRCK2
DOBCK2
106
CLOCK GEN.
BUFF
IC8006
Q8002
134
GIO14
95
127
GIO16
DSP_CLKS
DOMCK2
TO
AU.AD
VIDEO SYSTEM BLOCK DIAGRAM (2/2)
Содержание GR-D23EK
Страница 12: ...1 12 No YF008 Fig 13 17 48 49 S17a S17a NOTE17 BKT SPK BKT HINGE 45 S17a S17b 46 S17a 47 a a ...
Страница 22: ......