CTLAMPOUT
SB_GAIN
LSD
V.PULSE
TO
VIDEO/N. AUDIO
VIDEO_ENV
V.PULSE
X3301
TIMER CLOCK
(32kHz)
IC3301
(SYSTEM CONTROL MICROPROCESSOR)
LSB
LSD(LMC2)
LSC
TP4001
CTL.P
M
LSB
LSA
LSC
V.FF
6
65
64
X1
X2
X3302
MAIN SYSTEM
CLOCK
(10MHz)
69
67
OSC2(OUT)
OSC1(IN)
CFG
CAP.M_F/R
CAPPWM
LM_F/R/S(LMC1)
DFG
DRUMPWM
8
28
101
35
108
102
S_DET
SECAM_DET
MESECAM_DET
C.SYNC
26
27
LSA
25
36
1 2
D_PG+
D_PG-
L1
L2
CAP.M_FG
CAP.M_F/R
LM_F/R/S
DRUM_PG/FG
DRUM_VCTL
PHOTO
SENSOR
PC3002
54
55
SP_FG
TU_FG
SDA
SCL
6
5
IC3303
(SERIAL MEMORY)
76
75
I2C_DATA2
I2C_CLK2
73
TU_V.MUTE[H]
N.REC_ST[H]
N.REC[H]
VIDEO_ENV
SECAM_DET
C.SYNC
98
SB_GAIN(PWM)
MESECAM_DET
AL5V
REC_SAFETY
REC SAFETY SW
S3001
58
1
2
3
START_SENSOR
END_SENSOR
CTL_GAIN
24
Q4001
SW
J7201
SAT_CTL
Q7201
SW
Q3007
DRUM MOTOR
1 2
3 in 1 MDA
CAP MOTOR
M
4
9
10
11
1
12
CN3001
4
9
10
11
1
12
M
LOADING MOTOR
CAP.M_VCTL
MAIN (SYSCON)
N.REC[H]
N.REC_ST[H]
I2C_DATA_AV2
S_DET[H]
D.FF
I2C_CLK_AV2
A.MUTE_VHS[H]
JS3001
2
3
4
5
ROTARY
ENCODER
PHOTO
SENSOR
PC3001
START
SENSOR
Q3302
14
END
SENSOR
Q3303
15
12
81
13
110
38
100
11
90
105
I2C_DATA_AV2
I2C_CLK_AV2
A.MUTE_VHS[H]
I2C_CLK_AV2
A.MUTE_VHS[H]
I2C_DATA_AV2
50
49
74
A.FF
H.REC_ST[L]
A.FF
H.REC_ST[H]
99
88
A.ENV/ND[L]
A.ENV/ND[L]
22
TO
FMA
TO
TUNER
34
SW2-2
37
SW1-2
I2C_DATA2
I2C_CLK2
TU_MUTE2
SW2-2
SW1-2
IC3001
(SYSTEM CONTROL MICROPROCESSOR)
VHS SYSCON
OSD_CS
TO
ON SCREEN
I2C_DATA2
I2C_CLK2
S.DATA_FRSYTS
S.CLK
SYNC_DET[H]
P.MUTE[L]
53
52
S.CLK
S.DATA_FRSYS
72
SYNC_DET[H]
51
OSD_CS
103
P_MUTE[L]
RST
IC3302
(RESET IC)
1
66
RES
80
VHS_DATA_ON
59
VDR_DATA_ON
46
S_DATA_FRVDR
47
S_DATA_TOVDR
48
S_CLK_SYS
80
VHS_DATA_ON
79
VDR_DATA_ON
46
S_DATA_FRVDR
47
S_DATA_TOVDR
48
S_CLK_SYS
X3001
TIMER CLOCK
(32kHz)
65
64
X1
X2
X3002
MAIN SYSTEM
CLOCK
(10MHz)
69
67
OSC2(OUT)
OSC1(IN)
RST
IC3002
(RESET IC)
1
66
RES
SDA
SCL
6
5
IC3004
(SERIAL MEMORY)
76
75
I2C_DATA1
I2C_CLK1
60
TU_I2C_CLK1
61
TU_I2C_DATA1
73
TU_MUTE1
95
SW2-1
94
SW1-1
21
RF_AGC
20
AFC
34
P50_OUT
31
P50_IN
CN3102
3
2
1
Q3015 to Q3017
SW
TO
DISPLAY/SW
CN7001
BULE_LED
LED10
LED9
81
LED10
77
LED9
41
LED8_2
CN5311
5
TO SW REG.
FAN_CTL[H]
36
FAN_CTL
VDR SYSCON
CN3103
3
4
5
TO
JUNCTION
(VIDEO)
CN7102
6
7
8
12
13
25
93
A.MUTE_VDR[H]
AD_RST[L]
51
K_BUS_IN1
52
K_BUS_OUT1
54
K_BUS_REQ1
53
K_BUS_CLK1
55
E5_RESET[L]
72
P_MUTE[H]
KBUS_DATA_TOSYS
P.MUTE_VDR[H]
ADC_RESET[L]
A.MUTE_VDR[H]
SYS_RESET[L]
KBUS_CLK
KBUS_DATA_FRSYS
KBUS_REQ
RF_AGC
TU_I2C_DATA1
TU_I2C_CLK1
TU_MUTE1
SW2-1
SW1-1
AFC
I2C_DATA1
I2C_CLK1
I2C_CLK_AV1
I2C_DATA_AV1
SECAM[L]
AV1_YV_IN[H]
50
I2C_CLK_AV1
49
I2C_DATA_AV1
89
AV1_YC_IN[H]
18
SECAM[L]
83
A.MUTE[L]
90
VDR[H]
86
A_INPUT_SEL2
85
A_INPUT_SEL1
A.MUTE[L]
VDR[H]
A_INPUT_SEL2
A_INPUT_SEL1
TO
AUDIO I/O
TO
TERMINAL
CTL(+)
CTL(-)
CN2001
CN1
CTL HEAD (+)
CTL HEAD (-)
CTL
A/C HEAD
HEAD
A/C
3
1
CN7114
5
TO TERMINAL
P50_I/O
44
RMO
5 7
5 5
0 3
1 2
SW
5 8
2
1
2
1
WF1
WF2
WF3
WF4
WF5
SYSTEM CONTROL BLOCK DIAGRAM
2-69
2-70