2-4 (No.XA020SCH)
DDR_DQ0 to 15
DDR SDRAM
IC1602
DDR SDRAM section (SHEET 3)
IEEE1394 section (SHEET 2)
IEEE1394
terminal
IEEE1394
controller
IC1801
TPA+ TPA- TPB+ TPB-
PHY_RESET[L]
PHY_LREQ PHY_CLK
PHY_CNA PHY_CTL[0],[1]
PHY_DATA[0-7] PHY_LPS
PHY_LINK_ON
DDR SDRAM
IC1601
RA1613 to
RA1616
RA1609 to
RA1612
RA1625 to
RA1628
R1613 to
R1616
R1653 to
R1660
R1601 to
R1604
DDR_DQ16 to 31
SDRAM_DQ16 to 31
SDRAM_DQ0 to 15
SDRAM_A0 to 15
SDRAM_CKE
SDRAM_RAS_L
SDRAM_CAS_L
SDRAM_WE_L
SDRAM_DQM0 to 3
SDRAM_DQS0 to 3
SDRAM_CLK0,1
SDRAM_CLK_L0,1
DDR_CLK0,1
DDR_CLK_L0,1
DDR_DQM0 to 3
DDR_DQS0 to 3
DDR_CKE
DDR_RAS_L
DDR_CAS_L
DDR_WE_L
DDR_BA1,2
DDR_A0 to 12
CN4104
J4112
CN1801
Media processor (SHEET 4)
Media
processor
IC1401
IC1406
IC1407
ATA_DMAACK[L] ATA_INTRQ ATA_ADD1 to 4
ATA_DIOR[L] ATA_DIOW[L] ATA_IORDY
ATA_DAT0 to 15 ATA_RESET ATA_DMARQ
RD/WR[L] ALE OE[L]/LDS[L] MADD1 to 22 CS[0] F_PROT[H] E5_RESET[L]
SYS_RESET[L] VIDEO_RXD
K_BUS_CLK K_BUS_REQ K_BUS_IN/OUT
VIDEO_RST[L] SPI_MOSI SPI_CLK VIDEO_CS
ALE MADD6 to 21
65Mbit Flash
IC1201
MADD1 to 22
IC1202
IC1203
DMARQ IORDY CS1FX CS3FX
DIOW DIOR DMACK INT_ATA
ATA_DMARQ
ATA_IORDY ATA_INTRQ
ATA_DMAACK[L] ATA_ADD0 to 4
ATA_DIOW[L] ATA_DIOR[L]
FLASH-ROM section(SHEET 7)
TO
DVD
Recorder unit
ATAPI Interface section (SHEET 6)
20bit FET
Bas switch
IC2201
RSTATA
HD_AT0 to 15 ATA_A0 to 2
ATA_DATA0 to 15
P_CTL[H] ATA_RESET
CN2201
FET Bas switch
IC2202
RD/WR[L] E5_RESET[L] OE[L]/LDS[L] CS[0]
LH_AR6 to 21
Block diagrams
DIGITAL 0 2
Video signal control section (SHEET 5)
TO CN4101
SHEET 10
TO CN4102
SHEET 10
CN1001
CN1002
Video
controller
IC1001
16M SDRAM
IC1002
AO_FSYNC AO_D[0] DAC_RST[L]
AO_SCLK A_DAC_CS AO_MCLKO
DAC_SCL DAC_Y_OUT DAC_SDA
480I[H]
CIN VYIN SYNCDET CROUT CBOUT
YVOUT COUT RYOUT RCOUT
AP A0 to A9
UDQM WE
CAS RAS
DQ0 to DQ15
DAC_CVBS_OUT
DAC_SY_OUT
DAC_SC_OUT
VI_D2 to 9 VIDEO_RST[L] VO_D1 to 15 SPI_MOSI
VIDEO_27M VIDEO_CS VIDEO_MUTE[M] SPI_CLK VIDEO_RXD
SYS_RESET[L] K_BUS_CLK K_BUS_REQ K_BUS_IN K_BUS_OUT
AO_IEC958 AI_D[0] A_MUTE2[H] DAC_RST[L]
