JETWAY V333DAR1C, Руководство пользователя

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Item Help
PCI Master 1 WS Write Disabled
PCI Master 1 WS Read Disabled
CPU to AGP Post Write Disabled
PCI Delay Transaction Disabled
Menu Level >>
↑↓→←
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
3-7 Integrated Peripherals
CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
Integrated Peripherals
Item Help
> OnChip IDE Function Press Enter
> OnChip Device Function Press Enter
> Onboard Super IO Function Press Enter
Init Display First PCI Slot
Menu Level >
↑↓→←
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
OnChip IDE Function
Please refer to section 3-7-1
OnChip Device Function
Please refer to section 3-7-2
Onboard Super IO Function
Please refer to section 3-7-3
Init Display First
This item allows you to decide to activate whether PCI Slot or AGP VGA first. The settings
are: PCI Slot, AGP Slot.
3-7-1 OnChip IDE Function
CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
OnChip IDE Function