23
3-6-3 PCI Timing Settings
Phoenix – AwardBIOS CMOS Setup Utility
PCI Timing Settings
Item Help
PCI Master 1 WS Write Disabled
PCI Master 1 WS Read Disabled
CPU to PCI Post Write Enabled
PCI Delay Transaction Enabled
VLink Mode Selection BY Auto
VLink 8X Support Enabled
DRDY-Timing Slowest
Menu Level >>
↑↓→←
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
3-7 Integrated Peripherals
Phoenix – AwardBIOS CMOS Setup Utility
Integrated Peripherals
Item Help
OnChip IDE Function Press Enter
OnChip Device Function Press Enter
Onboard SIO Function Press Enter
Init Display First PCI Slot
Menu Level >
↑↓→←
Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
OnChip IDE Function
Please refer to section 3-7-1
OnChip Device Function
Please refer to section 3-7-2
Onboard SIO Function
Please refer to section 3-7-3
Init Display First
This item allows you to decide to activate whether PCI Slot or on-chip VGA first. The
settings are: PCI Slot, On-Chip VGA.