32
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
Video RAM Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result. The
settings are: Enabled and Disabled.
Memory Hole at 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this area
of system memory usually discusses their memory requirements. The settings are: Enabled
and Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
Memory Parity Check
This function provides parity check of memory.
The choice is either Disabled or Enabled.
3-6-1 Advanced DRAM Control
CMOS Setup Utility – Copyright(C) 1984-2000 Award Software
Advanced DRAM Control 1
Item Help
Auto Configuration Auto
SDRAM RAS Active Time 5T
SDRAM RAS Precharg Time 3T
RAS to CAS Delay 4T
Dram Background Command Delay 1T
LD-Off Dram RD/WR Cycles Delay 1T
Write Recovery Time 2T
VCM ACCT – ACT/REF Delay 9T
Early CKE Delay 1T Cntrl Normal
Early CKE Delay Adjust 7ns
Mem Command Output Time Delay 1T
SDRAM/VCM CAS Latency 3T
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