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iWave Systems Technologies Pvt. Ltd.
Zynq Ult MPSoC (ZU11/17/19EG) SOM DevKit Hardware User Guide
2.4
PS Interface Features
The features which are supported from Zynq Ult MPSoC (ZU11/17/19EG) PS is explained in the following
section.
2.4.1
PS-GTR Transceivers
The Zynq Ult MPSoC (ZU11/17/19EG) Carrier board supports different high speed interfaces through four PS-
GTR lanes (two from B2B-1 and two from B2B-2). Each PS-GTR lane is connected to High speed MUX/DEMUX IC to
support different high speed interfaces as mentioned below.
o
x1, x2, or x4 lane of PCIe at Gen1 (2.5Gb/s) or Gen2 (5.0Gb/s) rates
o
1 or 2 lanes of DisplayPort (TX only) at 1.62Gb/s, 2.7Gb/s, or 5.4Gb/s
o
1 SATA port at 1.5Gb/s, 3.0Gb/s, or 6.0Gb/s
o
1 USB3.0 port at 5.0Gb/s
The MUX/DEMUX connection and interface selection option is shown below for easy understanding. The selection
control of each MUX IC is connected to PS-GTR Lane selection 4bit DIP switch (SW6).
Figure 6: PS-GTR External Switch Connectivity.