REL 1.2
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iWave Systems Technologies Pvt. Ltd.
i.MX6 SODIMM SOM Hardware User Guide
2.7
i.MX6 Pin Multiplexing on SODIMM Edge
The i.MX6
CPU’s IO pins
have many alternate functions and can be configured to any one of the alternate functions based on the requirement. Also most of the i.MX6
CPU’s IO pins can be configured as GPIO if required.
The below table provides the details of i.MX6 CPU pin connections to the SOM edge connector with selected pin
function and available alternate functions. This table has been prepared by referring NXP
’s
i.MX6 Applications Processor Reference Manual.
Important Note: It is strongly recommended to use the pin function same as selected in the i.MX6 SOIDMM SOM Edge connector
for iWave’s BSP reusability and to have
compatible SODIMM modules in future for upgradability.
Table 6: IOMUX Configuration of i.MX6 SODIMM SOM Edge Connector interfaces
Interface/
Function
SODIMM
Edge Pin No
i.MX6 CPU
Pad Name
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
ALT8
ALT9
Default/
Reset State
Control
Signals
182
BOOT_MOD
E0
SRC_BOOT_
MODE0
184
BOOT_MOD
E1
SRC_BOOT_
MODE1
187
POR_B
SRC_POR_B
SD
107
SD3_DAT0
SD3_DATA0
UART1_CTS_
B
FLEXCAN2_T
X
GPIO7_IO04
GPIO7_IO04
111
SD3_DAT1
SD3_DATA1
UART1_RTS_
B
FLEXCAN2_R
X
GPIO7_IO05
GPIO7_IO05
112
SD3_DAT2
SD3_DATA2
GPIO7_IO06
GPIO7_IO06
114
SD3_DAT3
SD3_DATA3
UART3_CTS_
B
GPIO7_IO07
GPIO7_IO07
108
SD3_CMD
SD3_CMD
UART2_CTS_
B
FLEXCAN1_T
X
GPIO7_IO02
GPIO7_IO02
109
SD3_CLK
SD3_CLK
UART2_RTS_
B
FLEXCAN1_R
X
GPIO7_IO03
GPIO7_IO03
105
EIM_D25
EIM_DATA2
5
ECSPI4_SS3
UART3_RX_
DATA
ECSPI1_SS3
ECSPI2_SS3
GPIO3_IO25
AUD5_RXC
UART1_DSR
_B
EPDC_SDCE8
GPIO3_IO25