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IS31AP2121

Integrated Silicon Solution, Inc. – www.issi.com

22

Rev. C, 10/20/2015

I2C-BUS TRANSFER PROTOCOL

INTRODUCTION

IS31AP2121 employs I2C-bus transfer protocol. Two
wires, serial data and serial clock carry information
between the devices connected to the bus. Each
device is recognized by a unique 7-bit address and
can operate as either a transmitter or a receiver. The
master device initiates a data transfer and provides
the serial clock on the bus. IS31AP2121 is always
an I2C slave device.

PROTOCOL

START and STOP Condition

START is identified by a high to low transition of the
SDA signal. A START condition must precede any
command for data transfer. A STOP is identified by a
low to high transition of the SDA signal. A STOP
condition terminates communication between
IS31AP2121 and the master device on the bus. In
both START and STOP, the SCL is stable in the
high state.

Data Validity

The SDA signal must be stable during the high
period of the clock. The high or low change of SDA

only occurs when SCL signal is low. IS31AP2121
samples the SDA signal at the rising edge of SCL
signal.

Device Addressing

The master generates 7-bit address to recognize
slave devices. When IS31AP2121 receives 7-bit
address matched with 0110000 or 0110001
(ERRORB pin state during power up), IS31AP2121
will acknowledge at the 9th bit (the 8th bit is for R/W
bit). The bytes following the device identification
address are for IS31AP2121 internal sub-addresses.

Data Transferring

Each byte of SDA signaling must consist of 8
consecutive bits, and the byte is followed by an
acknowledge bit. Data is transferred with MSB first,
as shown in the figure below. In both write and read
operations, IS31AP2121 supports both single-byte
and multi-byte transfers. Refer to the figure below for
detailed data-transferring protocol.

Figure 35

Data Transferring

REGISTER DEFINITIONS

The IS31AP2121’s audio signal processing data flow is shown below. Users can control these functions by
programming appropriate settings in the register table. In this section, the register table is summarized first. The
definition of each register follows in the next section.

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Содержание IS31AP2121

Страница 1: ...cuit APPLICATIONS TV audio Boom box CD and DVD receiver docking system Powered speaker Wireless audio FEATURES 16 18 20 24 bits input with I2S Left alignment and Right alignment data format PSNR DR A weighting Loudspeaker 104dB PSNR 110dB DR 24V Multiple sampling frequencies FS 32kHz 44 1kHz 48kHz and 64kHz 88 2kHz 96kHz and 128kHz 176 4kHz 192kHz System clock 64x 128x 192x 256x 384x 512x 576x 768...

Страница 2: ...DB 1M 1M Micro Controller 1 F 1 F ERRORB MCLK BCLK LRCIN SDATA VCCLA VCCLB GNDL VCC 0 1 F 470 F VCCRA VCCRB GNDR VCC 0 1 F 0 1 F 0 1 F OUTRA OUTLB PBTL 1nF 1nF Speaker 4 15 H 6A BEAD 470pF BEAD 10 10 470pF 15 H 6A 220nF 100nF 100nF Note 4 Note 4 Note 2 1 23 24 25 19 14 15 21 20 22 36 39 2 3 44 47 48 35 34 41 37 38 46 13 27 9 28 8 Digital Audio Source 470 F Figure 2 Typical Application Circuit For ...

Страница 3: ...ggested using the choke with its IDC larger than 7A Note 2 These capacitors should be placed as close to speaker jack as possible and their values should be determined according to EMI test results Note 3 The snubber circuit can be removed while the VCC 20V Note 4 When concerning about short circuit protection or performance it is suggested using the choke with its IDC larger than 14A Note 5 2 1CH...

Страница 4: ...4 5 6 7 8 NC VCCLA OUTLA 9 10 11 12 VCCLB NC NC PBTL DGND NC NC DVDD NC NC NC 34 33 32 31 30 29 28 27 26 25 17 18 19 20 21 22 23 24 13 14 15 16 PDB BCLK SDATA 48 47 46 45 44 43 42 41 40 39 38 37 OUTLB NC GNDL GNDL NC NC CLK_OUT NC SCL NC LRCIN DVDD SDA ERRORB NC NC NC DGND NC RSTB OUTRA VCCLB NC VCCRB GNDR GNDR NC MCLK VCCRB VCCRA OUTRB 36 35 ...

Страница 5: ... during power up The other one is error status report low active It sets by register of A_SEL_FAULT at address 0x13 D6 to enable it This pin is monitored on the rising edge of reset A value of Low 15kΩ pull down sets the I2C device address to 0x30 and a value of High 15kΩ pull up sets it to 0x31 15 MCLK Master clock input Schmitt trigger TTL input buffer internal pull Low with an 80kΩ resistor 16 ...

Страница 6: ... Description Characteristics 34 41 VCCRB Right channel supply B 35 VCCRA Right channel supply A 36 OUTRB Right channel output B 37 38 GNDR Right channel ground 39 OUTRA Right channel output A 42 43 45 NC Not connected 46 OUTLB Left channel output B 47 48 GNDL Left channel ground Thermal Pad Connect to DGND ...

Страница 7: ...ion of this device specification before relying on any published information and before placing orders for products Integrated Silicon Solution Inc does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness...

Страница 8: ...PERATING CONDITIONS Symbol Parameter Condition Min Typ Max Unit VCC Supply for driver stage to VCCR L 10 26 V VDD Supply for digital circuit 3 15 3 45 V TJ Junction operating temperature 0 125 C TA Ambient operating temperature 0 70 C DC ELECTRICAL CHARACTERISTICS TA 25 C unless otherwise noted Symbol Parameter Condition Min Typ Max Unit IPDH VCC supply current during power down VCC 24V 10 200 µA ...

Страница 9: ...3mΩ C 220nF input is 1kHz sinewave volume is 0dB unless otherwise specified Symbol Parameter Condition Min Typ Max Unit PO RMS output power Note 2 THD N 0 16 VCC 24V 8dB volume 10 W THD N 0 25 VCC 24V 8dB volume 20 THD N 1 VCC 12V 8dB volume 7 5 THD N 10 VCC 12V 8dB volume 9 PBTL Mode VCC 24V RL 4Ω THD N 0 16 8dB volume 40 PBTL Mode VCC 12V RL 4Ω THD N 1 8dB volume 15 PBTL Mode VCC 12V RL 4Ω THD N...

Страница 10: ...and SCL signals receiving 300 20 0 1Cb 300 ns Cb Capacitive load for each bus line 400 400 pF VNL Noise margin at the low level for each connected device including hysteresis 0 1VDD 0 1VDD V VNH Noise margin at the high level for each connected device including hysteresis 0 2VDD 0 2VDD V I2S DIGITAL INPUT SWITCHING CHARACTERISTICS Note 4 Symbol Parameter Condition Min Typ Max Unit tLR LRCIN period...

Страница 11: ...IS31AP2121 Integrated Silicon Solution Inc www issi com 11 Rev C 10 20 2015 Figure 4 I2C Timing Figure 5 I2S Figure 6 Left Alignment Figure 7 Right Alignment Figure 8 System Clock Timing ...

Страница 12: ...IS31AP2121 Integrated Silicon Solution Inc www issi com 12 Rev C 10 20 2015 Figure 9 Timing Relationship Using I2S format as an example ...

Страница 13: ...Frequency Hz THD N 20 50 100 200 500 1k 2k 5k 20k 0 01 20 0 02 0 05 0 1 0 2 0 5 1 2 5 10 RL 4Ω VCC 24V 2 1CH Mode PO 5W PO 1W PO 2 5W Figure 14 THD N vs Frequency Frequency Hz THD N 20 50 100 200 500 1k 2k 5k 20k 0 01 20 0 02 0 05 0 1 0 2 0 5 1 2 5 10 RL 8Ω VCC 12V Strereo PO 0 5W PO 5W PO 2 5W Figure 11 THD N vs Frequency Frequency Hz THD N 20 50 100 200 500 1k 2k 5k 20k 0 01 20 0 02 0 05 0 1 0 2...

Страница 14: ...put Power W 0 01 20 0 02 0 05 0 1 0 2 0 5 1 2 5 10 50 10m 50m 100m 500m 1 2 5 10 20 RL 4Ω 2 1CH Mode f 1kHz VCC 12V VCC 24V VCC 18V Figure 20 THD N vs Output Power THD N Output Power W 0 01 20 0 02 0 05 0 1 0 2 0 5 1 2 5 10 50 10m 50m 100m 500m 1 2 5 10 20 VCC 12V RL 8Ω Strero 20Hz 1kHz 10kHz Figure 17 THD N vs Output Power THD N Output Power W 0 01 20 0 02 0 05 0 1 0 2 0 5 1 2 5 10 50 10m 50m 100...

Страница 15: ... 35 40 45 50 RL 8Ω Stereo VCC 24V VCC 18V VCC 15V VCC 8V VCC 12V Figure 26 Efficiency vs Output Power Power Saving Mode Crosstalk dB 20 20k 50 100 200 500 1k 2k 5k 10k Frequency Hz 120 0 100 80 60 40 20 VCC 12V RL 8Ω Stereo Left to Right Right to Left Figure 23 Cross Talk dBV Frequency Hz 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k 0k 120 110 100 90 80 70 60 50 40 30 20 10 0 10 20 VCC 24V RL 8Ω Stereo Fig...

Страница 16: ...50 60 RL 4Ω PBTL Mode THD N 1 THD N 10 Figure 28 Output Power vs Supply Voltage Note Dashed lines represent thermally limited region Output Power W Supply Voltage V 10 12 14 16 18 20 22 24 0 2 4 6 8 10 12 14 16 18 20 22 24 RL 4Ω 2 1CH Mode THD N 1 THD N 10 Figure 29 Output Power vs Supply Voltage Note Dashed lines represent thermally limited region ...

Страница 17: ...IS31AP2121 Integrated Silicon Solution Inc www issi com 17 Rev C 10 20 2015 FUNCTIONAL BLOCK DIAGRAM ...

Страница 18: ...pin is raised to high POWER DOWN CONTROL IS31AP2121 has a built in volume fade in fade out design for power down and mute function The relative power down timing diagrams for loudspeakers are shown below Figure 30 Power Down Timing Diagrams With Mute Figure 31 Power Down Timing Diagrams The volume level will be decreased to dB in several LRCIN cycles Once the fade out procedure is finished IS31AP2...

Страница 19: ...the VDD voltage is lower than 2 7V IS31AP2121 will turn off its loudspeaker power stages and cease the operation of digital processing circuits When VDD becomes larger than 2 8V IS31AP2121 will return to normal operation ANTI POP DESIGN IS31AP2121 will generate appropriate control signals to suppress pop sounds during initial power on off power down up mute and volume level changes 3D SURROUND SOU...

Страница 20: ...9 t10 t13 t14 t12 t5 t11 t3 I2C Active De mute Power On Normal Operation Normal Operation PDB L Figure 33 Power On Sequence Table 2 Power On Sequence Symbol Condition Min Max Unit t1 0 ms t2 0 ms t3 10 ms t4 0 ms t5 10 ms t6 10 ms t7 0 ms t8 200 ms t9 20 ms t10 0 1 ms t11 25 ms t12 25 ms t13 22 ms t14 0 1 ms POWER OFF SEQUENCE Hereunder is IS31AP2121 s power off sequence VCC VDD MCLK BCLK LRCIN RS...

Страница 21: ...licon Solution Inc www issi com 21 Rev C 10 20 2015 Table 3 Power Off Sequence Symbol Min t1 With I2C Control 35ms t1 Without I2C Control 5ms t2 0ms Note t3 0ms t4 1ms t5 1ms Note When t2 is less than 0 1ms pop noise may occur ...

Страница 22: ...e high or low change of SDA only occurs when SCL signal is low IS31AP2121 samples the SDA signal at the rising edge of SCL signal Device Addressing The master generates 7 bit address to recognize slave devices When IS31AP2121 receives 7 bit address matched with 0110000 or 0110001 ERRORB pin state during power up IS31AP2121 will acknowledge at the 9th bit the 8th bit is for R W bit The bytes follow...

Страница 23: ...eScal PreScal ASRC ASRC EQ1 EQ2 EQ1 EQ2 EQ7 EQ8 EQ7 EQ8 LCH RCH L R LRCIN BCLK SDATA PLL MCLK Surround Surroun Volume DRC1 Volume DRC1 Clipping 1 HPFdc PostScal 2 FIR S H2 SDM PWM Clipping 1 HPFdc PostScal 2 FIR S H2 SDM Power Stage OUTLA OUTRA OUTRB OUTLB LCH RCH I2C SCL SDA M32 M31 SUB EQ1 EQ2 EQ3 EQ4 HPF HPF Volume DRC2 Clipping 2 HPFdc PostScal 2 FIR S H2 SDM SUB LPF ...

Страница 24: ...dress Register 19 x000 0000 15h 23h User Defined Coefficients Register 20 24 24h Coefficients Control Register 25 xxxx 0000 25h 29h Reserved 2Ah Power Saving Mode Switching Level Register 26 xxx0 1101 2Bh Volume Fine Tune Register 27 0011 1111 Note The reserved registers are not allowed to write any bits in them or the IC will be abnormal Table 5 00h State Control 1 Register Bit D7 D5 D4 D3 Name I...

Страница 25: ...M3 Default 0 xxx 1 111 IS31AP2121 has mute function including master mute and channel mute When master mute is enabled all 3 processing channels are muted User can mute these 3 channels individually by channel mute When the mute function is enabled or disabled the fade out or fade in process will be initiated EN_CLK_OUT PLL Clock Output 0 Disabled 1 Enable MUTE Master Mute 0 All channel not muted ...

Страница 26: ... The IS31AP2121 provides bass management crossover frequency selection A 1st order high pass filter Channel 1 and 2 and a 2nd order low pass filter Channel 3 at selected frequency are performed XO Bass Management Crossover Frequency 0000 80Hz 0001 100Hz 0010 120Hz 0011 140Hz 0100 160Hz 0101 180Hz 0110 200Hz 0111 300Hz 1000 400Hz 1001 500Hz 1010 600Hz 1011 700Hz 1100 800Hz 1101 900Hz 1110 1000Hz 11...

Страница 27: ...master volume operation 1 Channel 1 2 s master volume bypass Table 14 0Dh Channel 3 Configuration Register Bit D7 D5 D4 D3 Name C3DRCM C3PCBP Default xxx 1 0 Bit D2 D1 D0 Name C3DRCBP C3HPFBP C3VBP Default 0 0 0 The IS31AP2121 can configure each channel to enable or bypass DRC and channel volume and select the limiter set IS31AP2121 support two mode of DRC RMS and PEAK detection which can be selec...

Страница 28: ... 1 Disable MCLK detect circuit QT_EN Power Saving Mode 0 Disable 1 Enable PWM_SEL PWM Modulation 0 Qua ternary 1 Ternary Table 17 12h VCC Under voltage Selection Register Bit D7 D6 D4 D3 D0 Name Dis_HVUV HV_UVSEL Default 1 xxx 0001 IS31AP2121 can disable HV under voltage detection via D7 IS31AP2121 support multi level HV under voltage detection via D3 D0 using this function IS31AP2121 will fade ou...

Страница 29: ...the coefficients in the RAM CFA Coefficient RAM Base Address Table 20 15h 17h User Defined Coefficients Registers Top Middle Bottom 8 bits of coefficients A1 Bit D7 D0 Name C1B Default Table 21 18h 1Ah User Defined Coefficients Registers Top Middle Bottom 8 bits of coefficients A2 Bit D7 D0 Name C2B Default Table 22 1Bh 1Dh User Defined Coefficients Registers Top Middle Bottom 8 bits of coefficien...

Страница 30: ...r volume fine tune is added to the individual channel volume fine tune as the total volume fine tune MV_FT Master Volume Fine Tune 00 0dB 01 0 125dB 10 0 25dB 11 0 375dB C1V_FT Channel 1 Volume Fine Tune 00 0dB 01 0 125dB 10 0 25dB 11 0 375dB C2V_FT Channel 2 Volume Fine Tune 00 0dB 01 0 125dB 10 0 25dB 11 0 375dB C3V_FT Channel 3 Volume Fine Tune 00 0dB 01 0 125dB 10 0 25dB 11 0 375dB RAM ACCESS ...

Страница 31: ...efficient B2 in I2C address 0X1F 13 Write bottom 8 bits of coefficient B2 in I2C address 0X20 14 Write top 8 bits of coefficient A0 in I2C address 0X21 15 Write middle 8 bits of coefficient A0 in I2C address 0X22 16 Write bottom 8 bits of coefficient A0 in I2C address 0X23 17 Write 1 to WA bit in address 0X24 Note the read and write operation on RAM coefficients works only if LRCIN Pin 15 switchin...

Страница 32: ...g table shows the power clipping level s numerical representation Table 28 Sample Calculation for Power Clipping Max Amplitude dB Linear Decimal Hex 3 21 Format VCC 0 1 2097152 200000 VCC 0 707 3 0 707 1482686 169FBE VCC 0 5 6 0 5 1048576 100000 VCC L x L 10 x 20 D 2097152 L H dec2hex D ATTACK THRESHOLD The IS31AP2121 provides power limited function When the input RMS exceeds the programmable atta...

Страница 33: ...121 receives any input signal that is more than the noise gate release level Noise gate release level is defined by 24 bit representation and is stored in RAM address 0X76 The following table shows the noise gate attack and release threshold level s numerical representation Table 30 Sample Calculation for Noise Gate Attack and Release Level Input Amplitude Linear Decimal Hex 1 23 Format 0dB 1 8388...

Страница 34: ... com 34 Rev C 10 20 2015 Table 31 Sample Calculation for DRC Energy Coefficient DRC Energy Coefficient dB Linear Decimal Hex 1 23 Format 1 0 1 8388607 7FFFFF 1 256 48 2 1 256 32768 8000 1 1024 60 2 1 1024 8192 2000 L x L 10 x 20 D 8388607 L H dec2hex D ...

Страница 35: ...x000000 0x3C Channel 2 EQ3 CH2EQ3A1 0x000000 0x0B CH1EQ3A2 0x000000 0x3D CH2EQ3A2 0x000000 0x0C CH1EQ3B1 0x000000 0x3E CH2EQ3B1 0x000000 0x0D CH1EQ3B2 0x000000 0x3F CH2EQ3B2 0x000000 0x0E CH1EQ3A0 0x200000 0x40 CH2EQ3A0 0x200000 0x0F Channel 1 EQ4 CH1EQ4A1 0x000000 0x41 Channel 2 EQ4 CH2EQ4A1 0x000000 0x10 CH1EQ4A2 0x000000 0x42 CH2EQ4A2 0x000000 0x11 CH1EQ4B1 0x000000 0x43 CH2EQ4B1 0x000000 0x12 ...

Страница 36: ...00000 0x24 CH1EQ8A2 0x000000 0x56 CH2EQ8A2 0x000000 0x25 CH1EQ8B1 0x000000 0x57 CH2EQ8B1 0x000000 0x26 CH1EQ8B2 0x000000 0x58 CH2EQ8B2 0x000000 0x27 CH1EQ8A0 0x200000 0x59 CH2EQ8A0 0x200000 0x28 Channel 3 EQ1 CH1EQ9A1 0x000000 0x5A Channel 3 EQ2 CH2EQ9A1 0x000000 0x29 CH1EQ9A2 0x000000 0x5B CH2EQ9A2 0x000000 0x2A CH1EQ9B1 0x000000 0x5C CH2EQ9B1 0x000000 0x2B CH1EQ9B2 0x000000 0x5D CH2EQ9B2 0x00000...

Страница 37: ... Channel 2 Prescale C2PRS 0x7FFFFF 0x6C Channel 1 Postscale C1POS 0x7FFFFF 0x6D Channel 2 Postscale C2POS 0x7FFFFF 0x6E Channel 3 Postscale C3POS 0x7FFFFF 0x6F CH1 2 Power Clipping PC1 0x200000 0x70 CH3 Power Clipping PC2 0x200000 0x71 CH1 2 DRC Attack Threshold DRC1_ATH 0x200000 0x72 CH1 2 DRC Release Threshold DRC1_RTH 0x80000 0x73 CH3 DRC Attack Threshold DRC2_ATH 0x200000 0x74 CH3 DRC Release ...

Страница 38: ...in to Tsmax ts 150 C 200 C 60 120 seconds Average ramp up rate Tsmax to Tp 3 C second max Liquidous temperature TL Time at liquidous tL 217 C 60 150 seconds Peak package body temperature Tp Max 260 C Time tp within 5 C of the specified classification temperature Tc Max 30 seconds Average ramp down rate Tp to Tsmax 6 C second max Time 25 C to peak temperature 8 minutes max Figure 39 Classification ...

Страница 39: ...IS31AP2121 Integrated Silicon Solution Inc www issi com 39 Rev C 10 20 2015 PACKAGE INFORMATION eLQFP 48 ...

Страница 40: ...d pattern complies to IPC 7351 2 All dimensions in MM 3 This document including dimensions notes specs is a recommendation based on typical circuit board manufacturing parameters Since land pattern design depends on many factors unknown eg user s board manufacturing specs user must determine suitability for use ...

Страница 41: ...lution Inc www issi com 41 Rev C 10 20 2015 REVISION HISTORY Revision Detail Information Date A Initial release 2015 07 07 B Update pin out exchange Pin 36 and Pin 39 2015 09 10 C 1 Update EC table 2 Add performance figures 2015 10 20 ...

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