IRT AVS-3170, Инструкция, Страница: 6 / 18

3170-avs.ib.rev5.doc page 6 of 16 16/10/2007
Switching Logic:
Control logic for each switcher module is performed by a Programmable Logic Array (PLA) which has been
programmed for the required operations. This component will only function correctly when loaded with the correct
program and is therefore only available through IRT.
Each module of the switcher group has two control connectors on its rear assembly.
They are labelled PL 4 and PL 5. For descriptive purposes, PL 4 is called the “input” connector and PL 5 the
“output” connector.
The pins on these connectors have the following functions:
PL 4 PL 5
1A +12 Vdc NC
1B Ground Ground
2A Data 4 Data 4
2B Data 3 Data 3
3A Data 2 Data 2
3B Data 1 Data 1
4A Data 0 Data 0
4B Switch pulse in Switch pulse out
5A Busy out Busy in
5B Unlatch in Unlatch out
The 5 bit codes on Pins 2A to 4A represent the input selected. This code is in BCD (Binary Coded Decimal) where
the Data 0 to 3 represent the binary numbers 0 to 9 (Inputs 1 to 10 if Data 4 is 0 or Inputs 11 to 20 if Data 4 is 1).
The
unlatch out signal is asserted by a switcher if any of its front panel switches is operated or if its unlatch in
signal is asserted. The presence of an unlatch in signal causes any switcher to release control of the data lines (if it
had control of them).
A switcher signals that it has control of the data lines by asserting
busy out . Busy out also ripples busy in .
The operation of a push-button ripples unlatch to modules farther down the chain, causing any of them with control
of the bus to release it, and in so doing clear the
busy line.
As soon as the requesting module sees its busy in line clear, it takes control of the bus and asserts its busy out . The
busy out signal then ripples up the chain causing any other modules release control (if they had it).
Sync path:
The switchers may be operated in either a local or remote sync mode in order to allow simultaneous switching of
different signals in multilevel applications.
This implies that the matrix will not switch until a sync pulse is received. When this is not provided externally, a
local sync needs to be provided.
The AVS-3170 generates a local sync by means of a free running oscillator followed by a (U 2). This provides
pulses approximately every 25 ms.
The “localsync” signal is passed to the PLA via link LK 4, which allows a choice of internal or external sync to the
switcher logic. The chosen sync is echoed to “vertout” which is available on the PL 5 remote connector for slaving
other switchers. See
Configuration section for details.
1B 2B 3B 4B 5B
1A 2A 3A 4A 5A