•
Device Clear (
DCL
):
In the
F0
through
F4
formats, Device Clear resets the Digital488/80A to its
power on default state, and pulses the Clear output line for approximately 50 microseconds.
If either channel is in the high-speed binary data format (
F5
), a
DCL
or
SDC
to either channel enables
the command interpreter on the channel in the
F5
mode, and then changes the format to
F0
. All other
parameters remain unchanged. In addition, the Clear output line is not pulsed by
DCL
or
SDC
when
either channel is in the
F5
mode. This is the only programmable method to exit the
F5
format.
•
Group Execute Trigger (
GET
):
When the Digital488/80A recognizes a
GET
on either channel, it
pulses the Trigger output lines on both channels for approximately 50 microseconds. The
Handshake
(
H
) command should be issued to the desired channel, if it is desired to pulse only one handshake line
(
H2
).
•
My Listen Address (
MLA
):
When the Digital488/80A is addressed to Listen in the
F0
through
F4
format, it accepts characters from the Active Talker and interprets these characters as commands and
command parameters.
In the high-speed binary format (
F5
), the command interpreter is disabled. The Digital488/80A treats
all bytes received as data to be output to the digital I/O ports. Each time it receives 5 bytes or detects
EOI
, it pulses the Data Strobe for approximately 15 microseconds. Data is expected in a PORT5,
PORT4, PORT3, PORT2, PORT1 sequence.
If only 2 bytes are received, with
EOI
asserted on the second byte, the Digital488/80A updates PORT5
with the first byte received, PORT4 with the second byte received, and pulses the Data Strobe. Since
the Digital488/80A treats all received characters as data, the
User Status
(
U
) command is not
recognized.
•
My Talk Address (
MTA
):
In
Data Ready
(
R
) mode
R0
, when the Digital488/80A is addressed to Talk,
the unit asserts Inhibit, reads the data from all ports, unasserts Inhibit, and outputs the data to the bus
in the format as defined by the
Format
(
F
),
Port
(
P
), and
Bus Input/Output
(
G
) commands. The output
bus terminators are appended to the output with the exception of the
F4
and
F5
formats. The
F4
format does not append terminators. The output format of
F5
is separately described. After output in
the
F0
through
F4
formats, the Digital488/80A must be readdressed to Talk to perform subsequent
reads.
In
Data Ready
(
R
) mode
R1
, the Digital488/80A waits for an EDR transition on the selected channel
before latching the data and formatting it for output. If the EDR line has changed state prior to being
addressed to Talk, the data read at the time of EDR is buffered for output when next addressed to Talk.
If EDR changes again before the previous EDR buffered data has been output, the Digital488/80A
generates an EDR Overrun error and ignores the EDR read request. After output in the
F0
through
F4
formats, the Digital488/80A must be readdressed to Talk to perform subsequent buffered output of
EDR captured data.
In
Data Ready
(
R
) mode
R2
, the Digital488/80A waits for an EDR transition on the selected channel
before latching the data and storing them in the internal data buffer. Up to 2000 readings may be
latched and stored. The EDR and Inhibit lines function in the same manner as in the
R1
mode. If an
attempt is made to store more than 2000 readings, the Digital488/80A generates an Overrun error.
After output in the
F0
through
F4
formats, the Digital488/80A must be readdressed to Talk to perform
subsequent buffered output of EDR captured data.
In any
Data Ready
(
R
) mode, the Digital488/80A can request status using the
User Status
(
U
)
command without affecting the data ports or the Inhibit line. After the requested status is output, the
presently programmed
R
mode returns.
EDR cannot be used to capture data in the high-speed binary format (
F5
). When addressed to Talk in
this format, it asserts Inhibit, reads the data from all ports, unasserts Inhibit, and outputs the binary
data to the bus with EOI asserted on the fifth byte. When the last data byte is transferred, the data is
read again in anticipation of another data transfer. If Inhibit is used to sequence external hardware,
this line pulses
N+1
times, where
N
is the number of total 5-byte data transfers. In this format, the
Digital488/80A does not have to be readdressed to Talk to read the ports multiple times.
With all
F
formats, the data is output in a PORT5, PORT4, PORT3, PORT2, PORT1 sequence.
Digital488/80A User’s Manual
Digital488/80A Operation 33
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