Open-Q™ 624A Development Kit
Open-Q™ 624A Development Kit User Kit
36
3.8.15
External Codec/GPIO Expansion Header J1
Figure 17 External Codec/GPIO Expansion Header J1
This header exposes GPIO and other signals not exposed or used elsewhere in the platform. It also supports
the use of an external audio codec/amplifier through I2S interfaces, as well as supplying power.
Table 3-13 External Codec/GPIO Expansion Header J1 Pin out
Description
Signal
Pin # Description
Signal
Pin #
BLSP1 bit 3 - SPI1_MOSI
(GPIO 0)
GPIO_0_BLSP1_SP
I_MOSI
J1[1]
GND
GND
J1[2]
BLSP1 bit 2 - SPI1_MISO
(GPIO 1)
GPIO_1_BLSP1_SP
I_MISO
J1[3]
PMIC GPIO 1 – Intended
use is for 9.6Mhz CODEC
MCLK (DIV_CLK2)
PM_GPIO_1_DIV_CLK
2
J1[4]
BLSP1 bit 1 - SPI1_CS or
I2C1_SDA
(GPIO 2)
GPIO_2_BLSP1_SP
I_CS_N
J1[5]
PMIC Multi-Purpose Pin 3
PM_MPP_3
J1[6]
BLSP1 bit 0 - SPI1_CLK
or I2C1_SCL
(GPIO 3)
GPIO_3_BLSP1_SP
I_CLK
J1[7]
MI2S Bus 1 – Data bit 3
(GPIO 95)
MI2S_1_D3
J1[8]
GND
GND
J1[9]
MI2S Bus 1 – Data bit 2
(GPIO 94)
MI2S_1_D2
J1[10]
GPIO 74 – Intended use
is for codec interrupt
input
WCD_INT
J1[11] GND
GND
J1[12]
Slimbus Data Bit 1 – For
Codec connection (GPIO
72)
B2B_SLIMBUS_DA
TA1
J1[13] MI2S Bus 1 – Data bit 1
(GPIO 88)
MI2S_1_D1
J1[14]
Slimbus Data Bit 0 – For
Codec connection (GPIO
71)
B2B_SLIMBUS_DA
TA0
J1[15] MI2S Bus 1 – Data bit 0
(GPIO 93)
MI2S_1_D0
J1[16]
Slimbus CLK– For Codec
connection (GPIO 70)
B2B_SLIMBUS_CL
K
J1[17] MI2S Bus 1 – WS (GPIO
92)
MI2S_1_WS
J1[18]
GND
GND
J1[19] MI2S Bus 1 – SCK (GPIO
91)
MI2S_1_SCK
J1[20]
