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Figure 23. Schematic Page 8
Decoupling designed to a 6A load step
Xilinx Reference Decoupling Network Impedance:
BOM-Optimized Decoupling Network Impedance:
Using KEMET's K-SIM capacitor simulation
software we find that the Xilinx design has
peak impedance of about 1.5 mOhm over
frequency. Iterating in the same tool we
derive a network with a similar figure, but
fewer components. This reduces the BOM
and simplifies PCB layout.
Both designs are under Ztarget = 3mOhm.
Title
Size
Document Number
Renesas KU060 Reference Design
Title
Size
Document Number
Renesas KU060 Reference Design
Title
Size
Document Number
Renesas KU060 Reference Design
