User Guide 083
UG083.0
July 25, 2016
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7
If the Vendor ID and Product ID are not visible, or if there are any
error messages, try the following actions:
• Verify that the evaluation board has power and that the USB
cable is connecting the evaluation board and the PC.
• Disconnect and then reconnect the USB cable. You should hear
two tones from the PC speakers when the USB device is
enumerated.
• Cycle the power to the board.
• Close all instances of the ISL76534 application and restart the
software. Restart the PC if necessary.
• If none of this works, try installing the software on a different
PC to isolate the cause to the PC versus the evaluation board.
PCB Layout Recommendations
Good Printed Circuit Board (PCB) layout is necessary for optimum
performance. The following are recommendations to achieve
optimum high frequency performance from your PCB.
• To optimize thermal performance, solder the ISL76534’s
exposed thermal pad to GND. PCB vias should be placed below
the device’s exposed thermal pad and connected to GND to
transfer heat away from the device (see “General PowerPAD
Design Considerations” in the
ISL76534
datasheet). If the
thermal pad is not connected to GND then it should be
electrically isolated.
• Maximize use of AC decoupled PCB layers. All signal I/O lines
should be routed over continuous ground planes (i.e., no split
planes or PCB gaps under these lines). Avoid vias in the signal
I/O lines.
• When testing, use good quality connectors and cables, match
cable types and keep cable lengths to a minimum.
• A minimum of two power supply decoupling capacitors are
recommended (typically 4.7µF and 0.1µF) per supply and
placed as close to the IC as possible. Avoid placing vias
between the capacitor and the device because vias add
unwanted inductance. Larger value capacitors can be placed
farther away (see
“PCB Layouts”
starting on
page 11
).
For optimal thermal performance, use vias to distribute heat
away from the IC and to a system power plane. Fill the thermal
pad area with vias that are spaced 3x their radius (typically),
center-to-center, from each other. The via diameters should be
kept small, but they should be large enough to allow solder
wicking during reflow. To optimize heat transfer efficiency, do not
connect vias using “thermal relief” patterns. Vias should be
directly connected to the plane with plated through-holes.
Connect all vias to the correct voltage potential (power plane)
indicated in the datasheet. For the ISL76534, the thermal pad
potential is ground (GND).
