R34UH0002EU0100 Rev.1.00
Page 6
Aug 16, 2022
ISL70002SEHEVAL3Z Evaluation Board Manual
2.1
Layout Guidelines
PCB design files are available on the
webpage for you to study or incorporate into your
design.
1. Use a six-layer PCB with 2 ounce (70µm) copper outer layers or an equivalent in more layers.
2. Two interior layers should be dedicated for PGND planes. In addition, place a square island of PGND on the
top layer directly underneath the body of the ISL70002SEH. Fill this area with vias to connect the top island to
the PGND planes for optimal electrical and thermal performance. The ISL70002SEHVFE parts have an
exposed metal bottom that can be soldered to the PCB. You may also use a thermal interface material such as
a Sil-Pad to ensure good thermal contact between the PCB and the IC, with or without an exposed metal
bottom.
3. Top and bottom layers should be used primarily for high-power traces ensuring the lowest impedance paths
between the input capacitors, the IC, the inductor, and the output capacitors. Where convenient, use the top
layer to connect the IC pins to the various small signal resistor and capacitors.
4. Connect all DGND and PGNDx pins to the PGND island under the part. Connect all PVINx pins to the input
power supply using the lowest resistance PCB layers (typically the top and bottom) if possible.
5. Locate a PVIN ceramic bypass capacitor as close as possible to each pair of PGNDx and PVINx pins on the
top of the PCB and connect them to the pins in the top layer.
6. Group the small signal components together near their pin(s) on U1. This should include the components that
touch pins 1-16 and 59-63.
7. Locate the output voltage resistive divider as close as possible to the FB pin of the IC. Run a VOUT sense route
from the top node of the divider directly to the positive terminal on the load. This route can be on any layer.
8. Enclose the small signal components in an AGND pour, and duplicate that pour on an interior layer. Connect
these together with multiple vias. Connect the AGND pin and passive component leads of the IC to this pour.
9. Connect the GND side of the VOUT capacitors to the PGND planes with a low impedance path back to the IC.
10. Run an AGND route from the copper pour all the way to the negative terminal of the load. Run this parallel to
the VOUT sense route that connects the FB divider to the load.
11. Use a small island of copper to connect the LXx pins of U1 to the inductor(s), L1 (and L2, if using two parallel
inductors), to minimize the routing capacitance that degrades efficiency. Separate the island from ground and
power planes as much as possible. This copper pattern may need to be replicated on multiple layers to reduce
the resistance.
12. Keep all signal traces as short as possible.
13. A small series snubber (R25 and C20) connected from the LXx pins to the PGNDx pins can be used to dampen
ringing on the LXx pins if desired.
14. For optimum thermal performance, place a pattern of vias on the top layer of the PCB directly underneath U1.
Connect the vias to the ground planes, which serve as a heatsink.
