Intersil ISL70002SEHEVAL1Z Скачать руководство пользователя страница 2

AN1732 Rev.1.00

Page 2 of 13

December 6, 2016

ISL70002SEHEVAL1Z

Quick Start

1. Toggle S1 to the down (OFF) position.
2. Turn on the power supply. Set the output voltage to 3.3V and 

set the output current limit to 20A. Turn off the power supply.

3. Connect the positive lead of the power supply to J1 and the 

negative lead of the power supply to J2.

4. Turn on the electronic load and set the output current to 6A.
5. Connect the positive lead of the electronic load to J39 and 

connect the negative lead of the electronic load to J40.

6. Configure one DMM to monitor the input voltage from TP7 to 

TP11.

7. Configure another DMM to monitor the output voltage from 

TP13 to TP11.

8. Connect Channel 1 of the oscilloscope to J6 (or from TP33 to 

TP28) to monitor the rectangular waveform on the LXx pins.

9. Connect Channel 2 of the oscilloscope to J14 (or from TP36 to 

TP37) to monitor the output voltage. Ripple voltage is 
customarily measured with 20MHz bandwidth limiting.

10. Toggle S1 to the up (ON) position.
11. Verify the output voltage is 1.0V ±3% and the frequency of the 

LXx waveform is 1MHz ±10%.

Layout Guidelines

1. Use an eight-layer PCB with 2 ounce (70µm) copper or 

equivalent in thinner layers.

2. Two layers should be dedicated for ground plane.
3. Top and bottom layers should be used primarily for signals, 

but can also be used to increase the VIN, VOUT, and ground 
planes as required.

4. Connect all AGND, DGND, and PGNDx pins directly to the 

ground plane. Connect all PVINx pins directly to the VIN 
portion of the power plane.

5. Locate ceramic bypass capacitors as close as possible to U1. 

Prioritize the placement of the bypass capacitors on the pins 
of U1 in the order shown: PVINx, REF, AVDD, DVDD, SS, EN, 
PGOOD.

6. Locate the output voltage resistive divider as close as 

possible to the FB pin of the IC. The top leg of the divider 
should connect directly to the load and the bottom leg of the 
resistive divider should connect directly to AGND. The junction 
of the resistive divider should connect directly to the FB pin.

7. Use a small island of copper to connect the LXx pins of U1 to 

the inductor(s), L1 and L2, to minimize the routing 
capacitance that degrades efficiency. Separate the island 
from ground and power planes as much as possible.

8. Keep all signal traces as short as possible.
9. A small series snubber (R

25

 and C

20

) connected from the LXx 

pins to the PGNDx pins may be used to dampen ringing on the 
LXx pins if desired.

10. For optimum thermal performance, place a pattern of vias on 

the top layer of the PCB directly underneath U1. Connect the 
vias to the ground planes, which serve as a heatsink. Thermal 
interface material such as a Sil-Pad should be used to fill the 
gap between the vias and the bottom of U1 to ensure good 
thermal contact. Using a Sil-Pad has the added benefit of 
raising the bottom of U1 from the PCB surface so that a slight 
bend can be added to the leads for strain relief.

Содержание ISL70002SEHEVAL1Z

Страница 1: ...or synchronized to a 500kHz to 1MHz 20 external clock Two ISL70002SEH ICs can be synchronized to each other in a master slave configuration providing nearly twice the output current while switching 18...

Страница 2: ...ground planes as required 4 Connect all AGND DGND and PGNDx pins directly to the ground plane Connect all PVINx pins directly to the VIN portion of the power plane 5 Locate ceramic bypass capacitors a...

Страница 3: ...C CASE TEMPERATURE FIGURE 7 EFFICIENCY vs LOAD vs OUTPUT VOLTAGE VIN 3 3V fSW 1MHz 25 C CASE TEMPERATURE 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 EFFICIENCY LOAD CURRENT A 1 0VOU...

Страница 4: ...L1Z immersed in a temperature calibrated liquid bath to ensure the notated IC case temperature Continued 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 EFFICIENCY LOAD CURRENT A 1 8VOU...

Страница 5: ...d in a temperature calibrated liquid bath to ensure the notated IC case temperature Continued 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 EFFICIENCY LOAD CURRENT A 1 8VOUT 1 5VOUT 1...

Страница 6: ...AN1732 Rev 1 00 Page 6 of 13 December 6 2016 ISL70002SEHEVAL1Z FIGURE 20 ISL70002SEHEVAL1Z BOARD SCHEMATIC ISL70002SEH...

Страница 7: ...25 KEMET Multilayer Cap C0805C682K2RAC C8 C9 2 6800pF 10 200V 805 CAP_0805 KEMET Multilayer Cap LTST C170CKT D1 1 SMD LTST_C170CKT LITEON AlGaAs on GaAs Red LED 1N5822US D2 0 SMD2 DIO_CASE_D 5B MICROS...

Страница 8: ...1206 GENERIC Thick Film Chip Resistor S0603CA1962BEZ R8 R10 2 19 6k 0 10 1 10W 603 RES_0603 State of the Art 25ppm Thin Film Chip Resistor S0603CA4021BEZ R9 R11 2 4 02k 0 10 1 10W 603 RES_0603 State o...

Страница 9: ...AN1732 Rev 1 00 Page 9 of 13 December 6 2016 ISL70002SEHEVAL1Z Board Layout FIGURE 21 TOP SIDE ASSEMBLY DRAWING FIGURE 22 TOP LAYER...

Страница 10: ...AN1732 Rev 1 00 Page 10 of 13 December 6 2016 ISL70002SEHEVAL1Z FIGURE 23 LAYER 2 FIGURE 24 LAYER 3 Board Layout Continued...

Страница 11: ...AN1732 Rev 1 00 Page 11 of 13 December 6 2016 ISL70002SEHEVAL1Z FIGURE 25 LAYER 4 FIGURE 26 LAYER 5 Board Layout Continued...

Страница 12: ...AN1732 Rev 1 00 Page 12 of 13 December 6 2016 ISL70002SEHEVAL1Z FIGURE 27 LAYER 6 FIGURE 28 LAYER 7 Board Layout Continued...

Страница 13: ...AN1732 Rev 1 00 Page 13 of 13 December 6 2016 ISL70002SEHEVAL1Z FIGURE 29 BOTTOM LAYER FIGURE 30 BOTTOM SIDE ASSEMBLY DRAWING Board Layout Continued...

Страница 14: ...e intended for developers skilled in the art designing with Renesas products You are solely responsible for 1 selecting the appropriate products for your application 2 designing validating and testing...

Страница 15: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Renesas Electronics ISL70002SEHEVAL1Z...

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