4
Figure 10 shows a simplified diagram highlighting the critical
areas of a PC board layout. This diagram and the following
material represent goals to work towards during the layout
phase. Goals will be compromised during the layout process
due to component placement and space constraints. The
following text reviews these layout considerations in more
detail.
Current Sampling
1. Place the current sampling or sense resistor as close as
possible to the upper MOSFET drains. This is important
since the added inductance and resistance increase the
impedance and result in a reduction in drain voltage during
high peak pulse currents.
2. Current sense is critical, especially at lower current levels
where the current comparator threshold voltage is lower. A
good Kelvin connection requires that the voltage sample
must be taken at the R
SENSE
resistor ends and not at the
planes that the resistor is connected.
3. The lines to the current sense resistor should be parallel
and run away from the PHASE or PWM signals to prevent
coupling of spikes to the current comparator input that may
delay or advance triggering of the comparator. Parallel rout-
ing will work towards equal exposure for both lines, so that
the comparator common mode rejection characteristic will
reduce the influence of coupled noise.
4. Place the current sense filter network near the controller.
This will help reduce extraneous inputs to the comparator.
Voltage Sampling
1. To obtain optimum regulation use the Kelvin connection
for the output voltage sample as shown on the Functional
System Schematic Diagram of Figure 10. The ground con-
nection, pin 9 of the ISL6560 should be connected to the
system ground at the load.
2. The two voltage sampling lines described in item 1 above
should also be routed away from any high current or high
pulse voltages such as the phase lines or pads. Doing this
will reduce the possibility of coupling undesired pulses into
the feedback signal and either modifying the output of the
error amplifier or, if of sufficient amplitude, spuriously trigger-
ing the current comparator by readjusting the threshold volt-
age.
Other Considerations
1. Keep the leads to the timing capacitor connected to pin
CT short and return the ground directly to pin 9.
2. When using a transistor to disable the converter by pulling
the CT pin to ground, place the transistor close to the CT pin
to minimize extraneous signal pickup.
3. As in all designs, keep decoupling networks near the pins
that must be decoupled. For example, the decoupling/filter
network on the FB input shown below. The series resistor
should be located next to the FB pin.
4. Large power and ground planes are critical to keeping
performance and efficiency high. Consider a 1m
Ω
resistance
in a 40A supply line. With 1.8V output, this results in slightly
over 2% power loss in a 72W supply.
ISL6560/62 Evaluation Board
FIGURE 10. SCHEMATIC DIAGRAM SHOWING ONLY ONE CHANNEL OF “IDEAL” COMPONENT PLACEMENT
HIP6601ECB
+V
CORE
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
PWRGD
REF
PWM1
PWM2
VCC
CS-
CS+
GND
VID4
VID3
VID2
VID1
VID0
CT
FB
COMP
1
2
3
4
8
7
6
5
PHASE
PVCC
VCC
LGATE
UGATE
BOOT
PWM
GND
{
INPUT
VID CODES
from
PROCSSOR
12V
ISL6560
{
+V
IN
Place Near Drains of the
Output Transistors
Keep Leads Together
& Away from Output
Try to return bypass
capacitors to ground
of lower MOSFETs
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